AD4697BCPZ datasheet(13/107 Pages) AD

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Data Sheet

AD4697/AD4698

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 13 of 107

Table 7. AD4697/AD4698 LFCSP Pin Function Descriptions

No.

Mnemonic.

Type1

Description

CNV

Convert Input. When the device is configured in conversion mode, a rising edge on CNV initiates a conversion of the selected analog

input. The AD4697/AD4698 can interface to a 4-wire SPI by tying CNV to CS. See the Digital Interface Operation section for more

information.

Chip Select Input. When configured in register configuration mode, CS frames SPI read and write transactions that access the

configuration registers. When the device is configured in conversion mode, CS can either be held low throughout the entire

conversion or used to frame SPI transactions that read back conversion results. The AD4697/AD4698 can interface to a 4-wire SPI

by tying CNV to CS. See the Digital Interface Operation section for more information.

REFGND

Reference Ground. REF is referenced to REFGND. IN0 to IN7 can be paired with REFGND to the ADC core to sample the

differential voltage between them. See the Channel Configuration Options section for a detailed description on pairing inputs.

REF

Reference Input. VREF must be provided by an external precision reference voltage between 2.4 V and 5.1 V. The REF pin must be

decoupled with a minimum 1 μF capacitor for optimal operation. See the Voltage Reference Input section for more information.

IN0

Analog Input 0.

EPAD

Exposed Pad. The exposed pad is not connected internally. For increased reliability of the solder joints, it is recommended that the

pad be soldered to the system ground plane.

1 AI is analog input, P is power, DI is digital input, DO is digital output, and NC is no internal connection.

Figure 3. AD4698 WLCSP Ball Configuration

Table 8. AD4698 WLCSP Ball Function Descriptions

Ball No.

Mnemonic

Type1

Description

SDI

Serial Data Input. When the device is configured in register configuration mode, SDI is used to perform SPI read and write

transactions to access the configuration registers. In conversion mode, SDI receives 5-bit commands from the digital host, as

shown in Table 18.

Chip Select Input. When configured in register configuration mode, CS frames SPI read and write transactions that accesses

the configuration registers. When the device is configured in conversion mode, CS can either be held low throughout the entire

conversion or used to frame SPI transactions that read back conversion results. The AD4697/AD4698 can interface to a 4-wire

SPI by tying CNV to CS. See the Digital Interface Operation section for more information.

REFIN

Internal Reference Buffer Input. The internal reference buffer can be used to buffer the reference voltage source and drive the

REF pin internally. When the internal reference buffer is enabled, REFIN must be driven by an external precision reference

source between 2.4 V and 5.1 V. When not using the internal reference buffer, REFIN must be tied to REF. See the Internal

Reference Buffer section for more information.

No Connect. Leave this pin open or connected to AGND.

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