BLC2425M10LS500P datasheet(3/10 Pages) AMPLEON

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BLC2425M10LS500P

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Product data sheet

Rev. 2 — 21 March 2019

3 of 10

BLC2425M10LS500P

Power LDMOS transistor

6. Characteristics

7. Test information

7.1 Ruggedness in class-AB operation

The BLC2425M10LS500P is capable of withstanding a load mismatch corresponding to

VSWR = 20 : 1 through all phases under the following conditions: VDS =32V;

IDq =20mA; PL = 500 W (CW); f = 2450 MHz.

7.2 Impedance information

[1]

ZS and ZL defined in Figure 1.

Table 6.

DC characteristics

Tj =25

°C, per section; unless otherwise specified.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

V(BR)DSS drain-source breakdown voltage VGS =0V; ID =2.7 mA

VGS(th)

gate-source threshold voltage

VDS = 32 V; ID = 20 mA 1.75

2.2

2.65

IDSS

drain leakage current

VGS = 0 V; VDS = 32 V

--4.2

μA

IDSX

drain cut-off current

VGS =VGS(th) + 3.75 V;

VDS =10V

59.3

IGSS

gate leakage current

VGS = 11 V; VDS = 0 V

--40

gfs

forward transconductance

VDS =10V; ID = 15.2 A -

RDS(on)

drain-source on-state resistance VGS =VGS(th) + 3.75 V;

ID = 10.64 A

45.5

Table 7.

RF characteristics

Test signal: CW pulsed at 2450 MHz; RF performance at VDS =32V; IDq = 10 mA per section;

Tcase =25

°C; unless otherwise specified; in a class-AB production test circuit.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

power gain

PL = 500 W

13.2

14.5 -

RLin

input return loss

PL = 500 W

−18 −5dB

ηD

drain efficiency

PL = 500 W

Table 8.

Typical impedance

Measured load-pull data half device. Typical values unless otherwise specified. IDq =20mA;

VDS =32V.

ZS [1]

ZL [1]

(MHz)

(

Ω)

(

Ω)

2400

2.95

− j6.51

2.3

− j2.6

2450

4.50

− j6.95

2.1

− j2.4

2500

5.58

− j5.66

2.2

− j2.2

BLC2425M10LS500P Datasheet(PDF) 3 Page - Ampleon Netherlands B.V.

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