DM9101
10/100Mbps Ethernet Physical Layer Single Chip Transceiver
Final
27
Version: DM9101-DS-F03
July 22, 1999
DAVICOM Specified Configuration Register (DSCR) - Register 16 (continued)
Bit
Bit Name
Default
Description
16.11
REPEATER
0, RW
Repeater/Node Mode:
1=Repeater mode
0=Node mode
In Repeater mode, the Carrier Sense (CRS) output from the
DM9101 will be asserted only by receive activity. In NODE
mode, or a mode not configured for Full Duplex operation, CRS
will be asserted by either receive or transmit activity.
The value of the RPTR/NODE input pin is latched into this bit at
power-up reset.
16.10
TX
1, RW
100Base-TX or FX Mode Control:
1=100Base-TX operation
0=100Base-FX operation
16.9
UTP
1, RW
UTP Cable Control:
1=The media is a UTP cable, 0=STP
16.8
CLK25MDIS
0, RW
CLK25M Disable:
1=CLK25M output clock signal tri-stated
0=CLK25M enabled
This bit should be set to 1 to disable the 25Mhz output and
reduce ground bounce and power consumption. For
applications requiring the CLK25M output, set this bit to 0.
16.7
F_LINK_100
0, RW
Force Good Link in 100Mbps:
0=Normal 100Mbps operation
1=Force 100Mbps good link status
This bit is useful for diagnostic purposes.
16.6
Reserved
1, RW
Reserved:
16.5
LINKLED_CTL
0, RW
LINKLED Mode Select:
0= Link LED output configured to indicate link status only
1= Link LED output configured to indicate traffic status: When
the link status is OK, the LED will be on. When the chip is in
transmitting or receiving, it flashes.
16.4
FDXLED_MODE
0, RW
FDXLED Mode Select:
1= FDXLED output configured to indicate polarity in 10Base-T
mode
0= FDXLED output configured to indicate Full Duplex mode
status for 10Mbps and 100Mbps operation
16.3
SMRST
0, RW
Reset State Machine:
When this bit is set to 1, all state internal machines will be
reset. This bit will clear after reset is completed.
16.2
MFPSC
0, RW
MF Preamble Suppression Control:
1= MF preamble suppression on
0= MF preamble suppression off
MII frame preamble suppression control bit
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