*1 Frequency limitations apply

*2 2ch can be used simultaneously

*3 For industrial/consumer use

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RENESAS RZ/A SERIES

Benefits of RZ/A1 Group, and RZ/A2M MPUs

Conventional MPU

5V/12V

5V/12V

Regulator

3.3V

Regulator

1.5V / 0.75V

Regulator

1.2V

Regulator

3.3V

NOR

Flash

DRAM

（DDR3）

SPI Flash

Conventional MPU

Regulator

1.2V

RZ/A1,A2M

Higher costs

Advantages

•No need to design a

high-speed interface

•Reduced mounting area

•Reduced PCB cost

•No DRAM procurement issues

•Reduced EMI noise

RZ/A1, A2M concept

■ Include on-chip graphics display and camera input capabilities

Page0

(2MB)

[1MB]

{512KB}

Page1

(2MB)

[1MB]

{512KB}

Page2

(2MB)

[1MB]

{512KB}

Page3

(2MB)

[1MB]

{512KB}

Page4

(2MB)

[1MB]

{1MB}

Video Display Controller ch1

(A1H and A1M only)

Video Display Controller ch0

Buffer

Use of graphics bus by

VDC to fetch multiple

layers of display data

Storage of input images

via graphics bus

Internal

Graphics bus

Page0

(2MB)

[1MB]

《512KB》

{512KB}

〈512KB〉

Page1

(2MB)

[1MB]

《512KB》

{512KB}

〈512KB〉

Page2

(2MB)

[1MB]

《1MB》

{512KB}

〈512KB〉

Page3

(2MB)

[1MB]

《1MB》

{512KB}

〈512KB〉

Page4

(2MB)

[1MB]

《1MB》

{1MB}

〈—〉

Large-capacity on-chip RAM

CPU

1

2

3

4

Integration of multiple layers of data and output to LCD

{

A1H (10MB)

A1M [5MB]

A2M

《4MB》

A1L, A1LU {3MB}

A1LC

〈2MB〉

■ Eliminate the need to design

a high-speed interface

■ Reduced mounting area

■ Reduced PCB cost

■ No DRAM procurement issues

■ Reduced EMI noise

Product Information

RZ/A1H, RZ/A1M

RZ/A1LU

RZ/A1L

RZ/A1LC

RZ/A2M

RZ/A3UL

CPU/Frequency

Cortex-A9/400MHz

Cortex-A9/528MHz

Cortex-A55/1.0GHz

On-Chip RAM

5MB / 10MB

3MB

2MB

4MB

128KB (w/ ECC)

Supported Flash

ROM

NAND

NOR,

Serial (DDR)

NOR,

Serial (SDR)

NOR, Serial (DDR), NAND,

HyperFlash, OctaFlash

Serial (DDR),

OctaFlash

RAM Interface

SDRAM

SDRAM, HyperRAM,

OctaRAM

DDR3L/DDR4, OctaRAM

Graphics Engine

2D (OpenVG)

Unavailable

2D, Sprite Engine

Unavailable

LCD Controller

VDC5 (2ch)

VDC5 (1ch)

VDC6 (1ch)

LCDC (1ch)

Camera

Interface

Digital (Parallel)Analog

Digital (Parallel)

Digital

(Parallel/Serial: MIPI)

Digital

(Serial: MIPI)

JPEG Codec Unit

Available

Unavailable

Available

Unavailable

Connectivity

2 x USB2.0(FS/HS)

2 x SDHI

1 x 10/100base Ethernet

2 x USB2.0 (FS/HS/OTG)

2 x SDHI (UHS-I)

1 x USB2.0 Host

1 x USB2.0 (Host/Function)

2x SDHI (UHS-I)

Package

256QFP, 324BGA,

176QFP, 208QFP,

176QFP, 208QFP,

For more information, visit www.renesas.com/rza

■ RZ/A2M MPUs with DRP improve image processing performance by 10X over RZ/A1 MPUs

– Dynamically Reconfigurable Processor (DRP) technology accelerates image processing

– Enables hybrid e-AI solutions with DRP for image processing + CPU for inference

Benefits of RZ/A3UL

■ 64bit CPU@1GHz RTOS MPU

■ Choice of two memory I/Fs for different applications

– Octal-SPI Flash/Octal-SPI RAM: For simple and low cost PCB design

– DDR3L/DDR4: For high resolution HMI and camera use cases

■ Pin-compatible RZ/A3UL (RTOS) and RZ/G2UL (Linux) for easy migration

– The 361-pin package is pin-compatible between RZ/A3UL and RZ/G2UL

Document Number: R01PF0230EU0100