CC2430-RTR1-F32Z datasheet(67/234 Pages) TI

67 / 234 page

CC2430

CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A

Page 67 of 232

MEMCTR (0xC7) – Memory Arbiter Control CC2430-F128

Bit

Name

Reset

R/W

Description

Not used

Unified memory mapping. When unified mapping is enabled, all

physical memories are mapped into the CODE memory space as

far as possible, when uniform mapping is disabled only flash

memory is mapped to CODE space

Disable unified mapping

MUNIF

R/W

Enable unified mapping

Flash bank map. Controls which of the four 32 KB flash memory

banks to map to program address 0x8000 – 0xFFFF in CODE

memory space.

Map program address 0x8000 – 0xFFFF to physical memory

address 0x00000 – 0x07FFF

Map program address 0x8000 – 0xFFFF to physical memory

address 0x08000– 0x0FFFF

Map program address 0x8000 – 0xFFFF to physical memory

address 0x10000 – 0x17FFF

5:4

FMAP[1:0]

R/W

Map program address 0x8000 – 0xFFFF to physical memory

address 0x18000 – 0x1FFFF

3:2

Not used

Flash cache disable. Invalidates contents of instruction cache and

forces all instruction read accesses to read straight from flash

memory. Disabling will increase power consumption and is

provided for debug purposes.

Cache enabled

CACHDIS

R/W

Cache disabled

R/W

Reserved. Always set to 1.

2 Reserved bits must always be set to the specified value. Failure to follow this will result in

indeterminate behaviour.

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