LIS3DHH datasheet(23/29 Pages) STMICROELECTRONICS

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LIS3DHH

7.5

CTRL_REG4 (23h)

Control register 4.

7.6

CTRL_REG5 (24h)

Control register 5.

Table 19. CTRL_REG5 register

Table 20. CTRL_REG5 register description

Table 16. CTRL_REG4 register

DSP_LP_

TYPE

DSP_BW_

SEL

ST2

ST1

PP_OD_

INT2

PP_OD_

INT1

FIFO_EN

1(1)

1. This bit must be set to ‘1’ for correct operation of the device.

Table 17. CTRL_REG4 register description

DSP_LP_TYPE

Digital filtering selection. Default value: 0

(0: FIR Linear Phase; 1: IIR Nonlinear Phase)

DSP_BW_SEL

User-selectable bandwidth. Default value: 0

(0: 440 Hz typ.; 1: 235 Hz typ.)

ST [2:1]

Self-test enable. Default value: 00

(00: Self-test disabled; Other: See Table 18)

PP_OD_INT2

Push-pull/open drain selection on INT2 pin. Default value: 0

(0: push-pull mode; 1: open drain mode)

PP_OD_INT1

Push-pull/open drain selection on INT1 pin. Default value: 0

(0: push-pull mode; 1: open drain mode)

FIFO_EN

FIFO memory enable. Default value: 0

(0: disabled; 1: enabled)

Table 18. Self-test mode selection

ST2

ST1

Self-test mode

Normal mode

Positive sign self-test

Negative sign self-test

Not allowed

0(1)

1. These bits must be set to ‘0’ for correct operation of the device.

0(1)

FIFO_SPI_HS_ON

Enables the SPI high speed configuration for the FIFO block that is used to

guarantee a minimum duration of the window in which writing operation of

RAM output is blocked. This bit is recommended for SPI clock frequencies

higher than 6 MHz. Default value: 0.

(0: not enabled; 1: enabled)

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