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STELPD01 Datasheet(PDF) 9 Page - STMicroelectronics |
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STELPD01 Datasheet(HTML) 9 Page - STMicroelectronics |
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9 / 27 page ![]() Figure 6. Delay time and VOUT ramp-up time 0 2 4 6 8 10 12 Time En/Fault VOUT delay time ramp -up time Table 8. Rise time vs. CdV/dt, VIN = 5 V CdV/dt [pF] 0 22 33 47 100 180 270 470 1000 Rise time [ms] 0.5 0.76 0.89 1.06 1.7 2.66 3.74 6.14 12.5 Note: Above table shows typical rise times obtained with available capacitor values. Values with Cdv/dt ≠ 0 are guaranteed by design/correlation and not tested in production. 6.2 Maximum load at startup Depending on supply voltage, load and output capacitance, it is possible that during startup the power dissipation reaches the maximum power protection and the output is shut down before the startup is completed. Increasing soft-start time, the inrush current is reduced and overtemperature fault is avoided. Adjustable soft-start time is very useful in those applications where a single power supply serves several loads connected to the same rail with a big equivalent capacitive load. Therefore, it is important to determine the right start-up time and in-rush current to limit the dynamic power stresses and avoid thermal shutdown during startup. 6.3 Normal operating condition The STELPD01 behaves like a power switch, buffering the circuitry on its output with the same voltage shown at its input, except for a small voltage fall due to the N-channel MOSFET RDSon. 6.4 Output voltage clamp This internal protection circuit clamps the output voltage to a maximum safe value, typically 17.5 V, if the input voltage exceeds the VCLAMP threshold. In this condition, the device regulates the output voltage, therefore power dissipation increases and according to load current, the thermal shutdown can occur. 6.5 Current limiting During operation, if the load current reaches the ILIM overload threshold, an overload is detected. The current limiting circuit opens the power MOSFET disconnecting the load. Typical reaction time of overcurrent control loop is 1.5 µs. This time considers the delay between the instant when output current reaches ILIM threshold and the activation of current control loop that acts on the gate of integrated FET to open the power path. On the latched versions (STELPD01), the EN/Fault pin of the device is automatically set to the intermediate voltage VI(INT), during Vout falling edge, in order to signal the overload event to the system controller. The device can be reset from this condition either by cycling the supply voltage or by pulling down the EN pin below the VIL threshold and then releasing it. STELPD01 Maximum load at startup DS13254 - Rev 1 page 9/27 |
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