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XIO2000 Datasheet(PDF) 108 Page - Texas Instruments |
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XIO2000 Datasheet(HTML) 108 Page - Texas Instruments |
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108 / 150 page  PCI Express Extended Configuration Space 96 November 2005 SCPS097B 5.11 Secondary Uncorrectable Error Mask Register The secondary uncorrectable error mask register controls the reporting of individual errors as they occur. When a mask bit is set to 1b, the corresponding error status bit is not set, PCI Express error messages are blocked, the header log is not loaded, and the first error pointer is not updated. See Table 5−9 for a complete description of the register contents. PCI Express extended register offset: 130h Register type: Read-only, Read/Write Default value: 0000 17A8h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 1 0 1 1 1 1 0 1 0 1 0 0 0 Table 5−9. Secondary Uncorrectable Error Mask Register Description BIT FIELD NAME ACCESS DESCRIPTION 31:14 RSVD R Reserved. Returns 00 0000 0000 0000 0000b when read. 13† BRIDGE_ERROR_MASK RW Internal bridge error. This mask bit is associated with a PCI-X error and has no effect on the bridge. 12† SERR_DETECT_MASK RW SERR assertion detected 0 = Error condition is unmasked 1 = Error condition is masked (default) 11† PERR_DETECT_MASK RW PERR assertion detected 0 = Error condition is unmasked (default) 1 = Error condition is masked 10† DISCARD_TIMER_MASK RW Delayed transaction discard timer expired 0 = Error condition is unmasked 1 = Error condition is masked (default) 9† UNCOR_ADDR_MASK RW Uncorrectable address error 0 = Error condition is unmasked 1 = Error condition is masked (default) 8† ATTR_ERROR_MASK RW Uncorrectable attribute error. This mask bit is associated with a PCI-X error and has no effect on the bridge. 7† UNCOR_DATA_MASK RW Uncorrectable data error 0 = Error condition is unmasked 1 = Error condition is masked (default) 6† SC_MSG_DATA_MASK RW Uncorrectable split completion message data error. This mask bit is associated with a PCI-X error and has no effect on the bridge. 5† SC_ERROR_MASK RW Unexpected split completion error. This mask bit is associated with a PCI-X error and has no effect on the bridge. 4 RSVD R Reserved. Returns 0b when read. 3† MASTER_ABORT_MASK RW Received master abort 0 = Error condition is unmasked 1 = Error condition is masked (default) 2† TARGET_ABORT_MASK RW Received target abort 0 = Error condition is unmasked (default) 1 = Error condition is masked 1† SC_MSTR_ABORT_MASK RW Master abort on split completion. This mask bit is associated with a PCI-X error and has no effect on the bridge. 0 RSVD R Reserved. Returns 0b when read. † These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset. |
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