CZ80CPU Megafunction Datasheet
Address Unit
This unit controls all operations on addresses (calculates the next instruction address, nested data address,
jump and return address etc.) and increments and decrements the 16-bit addr register. It includes pc_reg
(program counter), sp_reg (stack pointer), i_reg (interrupt register) and r_reg (refresh register).
NMI Control
This unit detects a falling edge on the nmin pin. If detected, the internal nmi register is set and this causes a
non-maskable interrupt service cycle.
Reset Control
This unit controls the state of external signal resetn. If it has value ‘0’ for at least three full clock cycles, then it
sets the internal synchronous reset signal (rst) to ‘1.’
Register Bank
This includes all the commonly used registers (based and alternative) and the logic element needed to change
the data in these registers.
Arithmetic-Logic Unit (ALU)
The unit accumulator and flag registers, and performs 8-bit arithmetic and logic operations, 16-bit arithmetic
operations (without increment and decrement), bit operations, and sets the flag register.
Verification Methods
The CZ80CPU core’s functionality was verified by means of a proprietary hardware modeler. The same stimulus
was applied to a hardware model that contained the original Zilog Z84C00 chip, and the results compared with
the core’s simulation outputs.
Device Utilization & Performance
The CZ80CPU is designed to run at frequencies up to 80 MHz on a typical 0.5-micron process and it uses less
than 8K gates depending on the technology. The CZ80CPU is a technology independent design that can be
implemented in a variety of process technologies.
Supported
Device
Utilization
Performance
Family
Tested
LEs
Memory
Memory bits
Fmax
Cyclone
EP1C6-6
3897
-
-
82 MHz
Stratix
EP1S10-5
3621
-
-
99 MHz
Stratix-II
EP2S15-3
3048
-
-
138 MHz
Note: Results optimized for speed
CAST, Inc.
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