MPC9351

MOTOROLA

TIMING SOLUTIONS

4

DC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = –40° to 85°C)

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

VIH

Input High Voltage

2.0

VCC + 0.3

V

LVCMOS

VIL

Input Low Voltage

0.8

V

LVCMOS

VPP

Peak-to-Peak Input Voltage

PCLK, PCLK

250

mV

LVPECL

VCMRa

Common Mode Range

PCLK, PCLK

1.0

VCC-0.6

V

LVPECL

VOH

Output High Voltage

2.4

V

IOH=-24 mAb

VOL

Output Low Voltage

0.55

0.30

V

V

IOL= 24 mA

IOL= 12 mA

ZOUT

Output Impedance

14 - 17

W

IIN

Input Leakage Current

±150

µA

VIN = VCC or GND

ICCA

Maximum PLL Supply Current

3.0

5.0

mA

VCCA Pin

ICCQ

Maximum Quiescent Supply Current

1.0

mA

All VCC Pins

a.

VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range

and the input swing lies within the VPP (DC) specification.

b.

The MPC9351 is capable of driving 50

Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated

transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines.

AC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = –40° to 85°C)a

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

fref

Input Frequency

÷ 2 feedback

÷ 4 feedback

÷ 8 feedback

Static test mode

100

50

25

0

200

100

50

300

MHz

MHz

MHz

MHz

PLL_EN = 1

PLL_EN = 1

PLL_EN = 1

PLL_EN = 0

fVCO

VCO Frequency

200

400

MHz

fMAX

Maximum Output Frequency

÷ 2 output

÷ 4 output

÷ 8 output

100

50

25

200

100

50

MHz

MHz

MHz

frefDC

Reference Input Duty Cycle

25

75

%

VPP

Peak-to-Peak Input Voltage PCLK, PCLK

500

1000

mV

LVPECL

VCMRb

Common Mode Range

PCLK, PCLK

1.2

VCC-0.9

V

LVPECL

tr, tf

TCLK Input Rise/Fall Time

1.0

ns

0.8 to 2.0V

t(

∅)

Propagation Delay (static phase offset)

TCLK to EXT_FB

PCLK to EXT_FB

–50

+25

+150

+325

ps

ps

PLL locked

PLL locked

tsk(o)

Output-to-Output Skew

150

ps

DC

Output Duty Cycle

100 – 200 MHz

50 – 100 MHz

25 – 50 MHz

45

47.5

48.75

50

50

50

55

52.5

51.75

%

%

%

tr, tf

Output Rise/Fall Time

0.1

1.0

ns

0.55 to 2.4V

tPLZ, HZ

Output Disable Time

10

ns

tPZL, ZH

Output Enable Time

10

ns

BW

PLL closed loop bandwidth

÷ 2 feedback

÷ 4 feedback

÷ 8 feedback

9.0 – 20.0

3.0 – 9.5

1.2 – 2.1

MHz

MHz

MHz

–3 db point of

PLL transfer

characteristic

tJIT(CC)

Cycle-to-cycle jitter

÷ 4 feedback

Single Output Frequency Configuration

10

22

ps

RMS value

tJIT(PER)

Period Jitter

÷ 4 feedback

Single Output Frequency Configuration

8.0

15

ps

RMS value

tJIT(

∅)

I/O Phase Jitter

4.0 – 17

ps

RMS value

tLOCK

Maximum PLL Lock Time

1.0

ms

a.

AC characteristics apply for parallel output termination of 50

Ω to VTT

b.

VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range

and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(

∅).

Freescale Semiconductor, Inc.

For More Information On This Product,

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