1

Block diagram and pin connection

Figure 1. Internal block diagram

DRIVER

HV CLAMP

COMPARATORS

TIMER

ADAPTIVE

CONTROL

CONTROL LOGIC

ON

ZCD

POWER

MANAGEMENT &

SWITCH OVER

GND

TON

DVS

GD

VAUX

VCC

TOFF

DIS/SYNC

Figure 2. Pin connections (top view)

VAUX

TOFF

TON

DVS

SO8

GD

DIS/SYNC

GND

VCC

1

2

3

4

5

6

7

8

Table 1. Pin functions

N.

Name

Function

1

DIS/

SYNC

This pin has two functions: disable and synchronization input.

•

Asynchronous turn-off of SR MOSFET always occurs after DIS pin voltage shows a positive rising edge

and the synchronous rectification stays disabled as long as it remains at the high level. If the DIS pin

voltage stays high for at least 4 switching cycles, the device enters low consumption mode.

•

Synchronization function requires that no external capacitor must be mounted between TON pin and GND,

so that SR MOSFET turn-off is accomplished by the positive rising edge of the applied SYNC signal or

when triggered by ZCD comparator output.

This pin is pulled high by internal current source (5 µA); if not used, it must be grounded.

2

GD

Gate driver output. Totem pole output stage is able to drive power MOSFET with high peak current levels. To

avoid excessive gate voltages in case the device is supplied with a high VCC, the high level voltage of this pin is

clamped to about 11.5 V. The pin must be connected directly to the SR MOSFET gate terminal.

3

GND

Return of the device bias current and return of the gate drive current. Route this pin close to the source terminal

of synchronous rectifier MOSFET.

SRK1001

Block diagram and pin connection

DS13155 - Rev 1

page 2/27