FXPS7115D4 datasheet(47/75 Pages) NXP

47 / 75 page

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

7.7.16 DEVSTAT_COPY - device status copy register (address 61h)

The device status copy register is a read-only register that contains a copy of the device

status information contained in the DEVSTAT register. See Section 7.7.2.1 "DEVSTAT

- device status register (address 01h)" for details regarding the DEVSTAT register

contents. A read of the DEVSTAT_COPY register has the same effect as a read of the

DEVSTAT register.

Bit

Symbol

DSP_ERR

reserved

COMM_ERR

MEMTEMP_ERR SUPPLY_ERR

TESTMODE

DEVRES

DEVINIT

Reset

Access

Table 80. DEVSTAT_COPY - device status copy register (address 61h) bit allocation

For bit descriptions, see Table 38.

7.7.17 SNSDATA0_L, SNSDATA0_H - sensor data #0 registers (address 62h, 63h)

The sensor data #0 registers are read-only registers that contain the 16-bit sensor

data. See Section 7.3.3.4 "Absolute pressure output data scaling equation" for details

regarding the 16-bit sensor data.

The SNSDATA0_H register value is latched on a read of the SNSDATA0_L register value

until the SNSDATA0_H register is read. To avoid data mismatch, the user is always

required to read the registers in sequence, SNSDATA0_L register first, followed by the

SNSDATA0_H register.

Location

Bit

Address

Symbol

62h

SNSDATA0_L

SNSDATA0_L[7:0]

63h

SNSDATA0_H

SNSDATA0_H[15:8]

Factory default

Access

Table 81. SNSDATA0_L, SNSDATA0_H - sensor data #0 registers (addresses 62h, 63h) bit allocation

7.7.18 SNSDATA1_L, SNSDATA1_H - sensor data #1 registers (address 64h, 65h)

The sensor data #1 registers are read-only registers that contain the 16-bit sensor

data. See Section 7.3.3.4 "Absolute pressure output data scaling equation" for details

regarding the 16-bit sensor data. The SNSDATA1 registers are beneficial for I2C read

wrap around to reduce the number of I2C transactions. In this case, the temperature can

be selected to be put into this register. See Table 9 and Table 67.

The SNSDATA1_H register value is latched on a read of the SNSDATA1_L register value

until the SNSDATA1_H register is read. To avoid data mismatch, the user is always

required to read the registers in sequence, SNSDATA1_L register first, followed by the

SNSDATA1_H register.

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 6 June 2022

47 / 75

FXPS7115D4 Datasheet(PDF) 47 Page - NXP Semiconductors

FXPS7115D4 Datasheet(HTML) 47 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75

Datasheet Download

Link URL