 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ATF1504ASV Datasheet(PDF) 1 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
ATF1504ASV Datasheet(HTML) 1 Page - Microchip Technology |
|
|
1 / 30 page  2019 Microchip Technology Inc. DS20006185A-page 1 ATF1504ASV/ATF1504ASVL Features • High-Density, High-Performance, Electri- cally-Erasable Complex Programmable Logic Device: - 3.0V to 3.6V operating range - 64 macrocells - 5 product terms per macrocell, expandable up to 40 per macrocell - 44 and 100 pins - 15 ns maximum pin-to-pin delay - Registered operation up to 77 MHz - Enhanced routing resources • In-System Programmability (ISP) via JTAG • Flexible Logic Macrocell: - D/T/Latch configurable flip-flops - Global and individual register control signals - Global and individual output enable - Programmable output slew rate - Programmable output open-collector option - Maximum logic utilization by burying a regis- ter with a COM output • Advanced Power Management Features: - Automatic 5 µA Standby (ATF1504ASVL) - Pin-controlled 100 µA Standby mode (typical) - Programmable pin-keeper circuits on inputs and I/Os - Reduced-power feature per macrocell • Available in Industrial Temperature Range • Robust EEPROM Technology: - 100% tested - Completely reprogrammable - 10,000 Program/Erase cycles - 20-year data retention - 2000V ESD protection - 200 mA latch-up immunity • JTAG Boundary-Scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported • PCI-Compliant • Security Fuse Feature • Green (Pb/Halide-Free/RoHS Compliant) Package Options Enhanced Features • Improved Connectivity (Additional Feedback Routing, Alternate Input Routing) • Output Enable Product Terms • Transparent-Latch Mode • Combinatorial Output with Registered Feedback within any Macrocell • Three Global Clock Pins • ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O • Fast Registered Input from Product Term • Programmable “Pin-keeper” Option •VCC Power-Up Reset Option • Pull-Up Option on JTAG Pins (TMS and TDI) • Advanced Power Management Features: - Edge-controlled power-down (ATF1504ASVL) - Individual macrocell power option - Disable ITD on global clocks Packages • 44-Lead PLCC • 44-Lead and 100-Lead TQFP Description The ATF1504ASV(L) is a high-performance, high-den- sity complex programmable logic device (CPLD) that utilizes Microchip’s proven electrically-erasable mem- ory technology. With 64 logic macrocells and up to 68 inputs and I/Os, it easily integrates logic from sev- eral TTL, SSI, MSI, LSI and classic PLDs. The ATF1504ASV(L)’s enhanced routing switch matrices increase usable gate count and the odds of successful pin-locked design modifications. The ATF1504ASV(L) has up to 64 bidirectional I/O pins and four dedicated input pins, depending on the type of device package selected. Each dedicated pin can also serve as a global control signal (register clock, register Reset or output enable). Each of these control signals can be selected for use individually within each macrocell. ATF1504ASV(L) 3.3V 64-Macrocell CPLD Data Sheet |
Similar Part No. - ATF1504ASV |
|
Similar Description - ATF1504ASV |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
British ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
