Advanced Clock Drivers Device Data

Freescale Semiconductor

3

MPC9773

Table 1. Pin Configuration

Pin

I/O

Type

Function

CCLK0

Input

LVCMOS

PLL reference clock

CCLK1

Input

LVCMOS

Alternative PLL reference clock

PCLK, PCLK

Input

LVPECL

Differential LVPECL reference clock

FB_IN

Input

LVCMOS

PLL feedback signal input, connect to an QFB

CCLK_SEL

Input

LVCMOS

LVCMOS clock reference select

REF_SEL

Input

LVCMOS

LVCMOS/PECL reference clock select

VCO_SEL

Input

LVCMOS

VCO operating frequency select

PLL_EN

Input

LVCMOS

PLL enable/PLL bypass mode select

MR/OE

Input

LVCMOS

Output enable/disable (high-impedance tristate) and device reset

FSEL_A[0:1]

Input

LVCMOS

Frequency divider select for bank A outputs

FSEL_B[0:1]

Input

LVCMOS

Frequency divider select for bank B outputs

FSEL_C[0:1]

Input

LVCMOS

Frequency divider select for bank C outputs

FSEL_FB[0:2]

Input

LVCMOS

Frequency divider select for the QFB output

INV_CLK

Input

LVCMOS

Clock phase selection for outputs QC2 and QC3

STOP_CLK

Input

LVCMOS

Clock input for clock stop circuitry

STOP_DATA

Input

LVCMOS

Configuration data input for clock stop circuitry

QA[0-3]

Output

LVCMOS

Clock outputs (Bank A)

QB[0-3]

Output

LVCMOS

Clock outputs (Bank B)

QC[0-3]

Output

LVCMOS

Clock outputs (Bank C)

QFB

Output

LVCMOS

PLL feedback output. Connect to FB_IN.

QSYNC

Output

LVCMOS

Synchronization pulse output

GND

Supply

Ground

Negative power supply

Supply

PLL positive power supply (analog power supply). It is recommended to use an external RC

Supply

supply for correct operation

Table 2. Function Table (Configuration Controls)

Control

Default

0

1

REF_SEL

1

Selects CCLKx as the PLL reference clock

Selects the LVPECL inputs as the PLL

reference clock

CCLK_SEL

1

Selects CCLK0

Selects CCLK1

VCO_SEL

1

Selects VCO

÷ 2. The VCO frequency is scaled by a factor of 2 (low VCO

frequency range).

Selects VCO

÷ 1 (high VCO frequency

range)

PLL_EN

1

Test mode with the PLL bypassed. The reference clock is substituted for the

internal VCO output. MPC9773 is fully static and no minimum frequency limit

applies. All PLL related AC characteristics are not applicable.

Normal operation mode with PLL

enabled.

INV_CLK

1

QC2 and QC3 are in phase with QC0 and QC1

QC2 and QC3 are inverted (180° phase

shift) with respect to QC0 and QC1

MR/OE

1

Outputs disabled (high-impedance state) and device is reset. During reset/

output disable the PLL feedback loop is open and the internal VCO is tied to

its lowest frequency. The MPC9773 requires reset after any loss of PLL lock.

Loss of PLL lock may occur when the external feedback path is interrupted.

The length of the reset pulse should be greater than one reference clock

cycle (CCLKx). The device is reset by the internal power-on reset (POR)

circuitry during power-up.

Outputs enabled (active)

VCO_SEL, FSEL_A[0:1], FSEL_B[0:1], FSEL_C[0:1], FSEL_FB[0:2] control the operating PLL frequency range and input/output frequency

ratios. See Table 3 to Table 6 and the Applications Section for supported frequency ranges and output to input frequency ratios.