Philips Semiconductors

Product specification

74F169

4-bit up/down binary synchronous counter

2

1996 Jan 05

853–0350 16190

FEATURES

DESCRIPTION

The 74F169 is a 4-bit synchronous, presettable Modulo 16 up/down

counter featuring an internal carry look-ahead for applications in

high-speed counting designs. Synchronous operation is provided by

having all flip-flops clocked simultaneously so that the outputs

change coincident with each other when instructed by the Count

Enable inputs and internal gating. This mode of operation eliminates

the output spikes which are normally associated with asynchronous

(ripple clock) counters. A buffered clock input triggers the flip-flops

on the Low-to-High transition of the clock.

The counter is fully programmable; that is, the outputs may be

preset to either level.

Presetting is synchronous with the clock and takes place regardless

of the levels of the Count Enable inputs. A Low level on the Parallel

Enable (PE) input disables the counter and causes the data at the

transition of the clock.

The direction of counting is controlled by the Up/Down (U/D) input; a

High will cause the count to increase, a Low will cause the count to

decrease.

The carry look-ahead circuitry provides for n-bit synchronous

applications without additional gating. Instrumental in accomplishing

this function are two Count Enable inputs (CET

Terminal Count (TC) output. Both Count Enable inputs must be Low

to count. The CET input is fed forward to enable the TC output. The

TC output thus enabled will produce a Low output pulse with a

output. The Low level TC pulse is used to enable successive

cascaded stages.

PIN CONFIGURATION

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

VCC

TC

Q0

Q1

Q2

Q3

CET

PE

U/D

CP

D0

D1

D2

D3

CEP

GND

SF00766

TYPE

TYPICAL

SUPPLY CURRENT

(TOTAL)

74F169

115MHz

35mA

ORDERING INFORMATION

ORDER CODE

DESCRIPTION

COMMERCIAL RANGE

PKG

DWG #

16-pin plastic DIP

N74F169N

SOT38-4

16-pin plastic SO

N74F169D

SOT109-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

DESCRIPTION

74F(U.L.)

HIGH/LOW

LOAD VALUE

HIGH/LOW

Parallel data inputs

1.0/1.0

20

µA/0.6mA

CEP

Count Enable parallel input (active Low)

1.0/1.0

20

µA/0.6mA

CET

Count Enable Trickle input (active Low)

1.0/2.0

20

µA/1.2mA

CP

Clock input (active rising edge)

1.0/1.0

20

µA/0.6mA

PE

Parallel Enable input (active Low)

1.0/1.0

20

µA/0.6mA

U/D

Up/Down count control input

1.0/1.0

20

µA/0.6mA

Flip-flop outputs

50/33

1.0mA/20mA

TC

Terminal count output (active Low)

50/33

1.0mA/20mA

NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20

µA in the High state and 0.6mA in the Low state.