Philips Semiconductors

Product specification

74F657

Octal transceiver with 8-bit parity generator/checker

2

90 July 30

853 1117 00081

FEATURES

high and low states)

DESCRIPTION

The 74F657 is an octal transceiver featuring non–inverting

buffers with 3–state outputs and an 8–bit parity

generator/checker, and is intended for bus–oriented

applications. The buffers have a guaranteed current sinking

capability of 24mA at the A ports and 64mA at the B ports.

The transmit/receive (T/R) input determines the direction of

the data flow through the bidirectional transceivers.

Transmit (active high) enables data from A ports to B ports;

receive (active low) enables data from B ports to A ports.

The output enable (OE) input disables both the A and B ports by

placing them in a high impedance condition when the OE input is

high

.

The parity select (ODD/EVEN) input gives the user the option of

odd or even parity systems

.

The parity (PARITY) pin is an output from the generator/checker

when transmitting from the port A to B (T/R = high) and an input

when receiving from port B to A port ( T/R = low).

When transmitting (T/R = high) the parity select (ODD/EVEN) input

is set, then the A port data is polled to determined the number of

high bits. The parity (PARITY) output then goes to the logic state

determined by the parity select (ODD/EVEN) setting and by the

number of high bits on port A.

For example, if the parity select (ODD/EVEN) is set low (even

parity), and the number of high bits on port A is odd, then the parity

(PARITY) output will be high, transmitting even parity. If the number

of high bits on port A is even, then the parity (PARITY) output will

be low, keeping even parity.

When in receive mode (T/R = low) the B port is polled to determine

the number of high bits. If parity select (ODD/EVEN) is low (even

parity) and the number of highs on port B is:

(1) odd and the parity (PARITY) input is high, then ERROR will be

high, significantly no error.

(2) even and the parity (PARITY) input is high, then ERROR will be

asserted low, indicating an error.

TYPE

TYPICAL PROPAGA-

TION DELAY

TYPICAL SUPPLY

CURRENT( TOTAL)

74F657

8.0ns

100mA

ORDERING INFORMATION

ORDER CODE

COMMERCIAL RANGE

INDUSTRIAL RANGE

DESCRIPTION

PKG DWG #

24–pin plastic slim

DIP (300mil)

N74F657N

I74F657N

SOT222-1

24–pin plastic SOL

N74F657D

I74F657D

SOT137-1

24–pin plastic SSOP

N74F657DB

I74F657DB

SOT340-1

INPUT AND OUTPUT LOADING AND FAN OUT TABLE

PINS

DESCRIPTION

74F (U.L.)

HIGH/LOW

LOAD VALUE

HIGH/LOW

A0 – A7

A ports 3–state inputs

3.5/0.117

70

µA/70µA

B0 – B7

B ports 3–state inputs

3.5/0.117

70

µA/70µA

PARITY

Parity input

3.5/0.117

70

µA/70µA

T/R

Transmit/receive input

2.0/0.066

40

µA/40µA

ODD/EVEN

Parity select input

1.0/0.033

20

µA/20µA

OE

Output enable input (active low)

2.0/0.066

40

µA/40µA

A0 – A7

A ports 3–state outputs

150/40

3.0mA/24mA

B0 – B7

B ports 3–state outputs

750/106.7

15mA/64mA

PARITY

Parity output

750/106.7

15mA/64mA

ERROR

Error output

750/106.7

15mA/64mA

Note to input and output loading and fan out table

1. One (1.0) FAST unit load is defined as: 20

µA in the high state and 0.6mA in the low state.