SLD-2000 10-2700 MHz 12 Watt LDMOS FET - Bare Die

303 S. Technology Court

Phone: (800) SMI-MMIC

http://www.sirenza.com

Broomfield, CO 80021

2

EDS-104292 Rev C

Pad #3

Backside Source = Ground

ESD

Protection

Pad #1

Gate

Manifold

Pad #2

Drain

Manifold

Contact Description

Pad #

Function

Description

1

Gate

Aluminum metallized manifold MOSFET Gate with ESD protection structure. (Topside contact)

2

Drain

Aluminum metallized manifold MOSFET Drain. (Topside contact)

3

Source

Chrome Gold metallized MOSFET Source contact. Appropriate electrical, mechanical and thermal connection required for

proper operation.

(Backside contact)

Absolute Maximum Ratings

Parameters

Value

Unit

Volts

20

Volts

RF Input Power

+33

dBm

Load Impedance for Continuous Operation

Without Damage

10:1

VSWR

Output Device Channel Temperature

+200

ºC

Storage Temperature Range

-40 to +150

ºC

Operation of this device beyond any one of these limits may cause

permanent damage. For reliable continuous operation see typical

setup values specified in the table on page one.

Caution: ESD Sensitive

Appropriate precaution in handling, packaging

and testing devices must be observed.

Quality Specifications

Parameter

Description

Unit

Typical

ESD Rating

Human Body Model

Volts

750

MTTF

Hours

Pad Diagram

Note 1:

Gate voltage must be applied to to the device

concurrently or after application of drain voltage to

prevent potentially destructive oscillations. Bias voltages should

never be applied to the transistor unless it is properly termi-

nated on both input and output.

Note 2:

device to device due to the normal die-to-die variation in thresh-

old voltage with LDMOS transistors.

Note 3:

device temperature. External temperature compensation may

be required. See Sirenza application notes AN-067 LDMOS

Bias Temperature

Compensation.