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HC05V7GRS/D Datasheet(PDF) 145 Page - NXP Semiconductors |
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HC05V7GRS/D Datasheet(HTML) 145 Page - NXP Semiconductors |
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145 / 170 page  SECTION 15: MESSAGE DATA LINK CONTROLLER Page 131 MC68HC05V7 Specification Rev. 1.0 When the MDLC is in the MDLC Stop or MDLC Wait mode of operation, and network activity is sensed, a CPU interrupt request will be generated. As part of the service routine for this interrupt, the programmer should once again assert the PSEN output. Note that both VCCA and VDD for the MDLC must be maintained in the MDLC Stop and MDLC Wait modes of operation in order for this to work properly. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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