HC05V7GRSSLASHD datasheet(97/170 Pages) NXP

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SECTION 14: SERIAL PERIPHERAL INTERFACE

Page 83

MC68HC05V7 Specification Rev. 1.0

SECTION 14

SERIAL PERIPHERAL INTERFACE

The Serial Peripheral Interface (SPI) is an interface which allows several MC68HC05

MCUs, or MC68HC05 MCU plus peripheral devices, to be interconnected within a single

printed circuit board. In an SPI, separate wires are required for data and clock. In the SPI

format, the clock is not included in the data stream and must be furnished as a separate

signal. An SPI system may be configured in one containing one master MCU and several

slave MCUs, or in a system in which an MCU is capable of being a master or a slave.

Features include:

•

Full duplex, three-wire synchronous transfers

•

Master or slave operation

•

Internal MCU clock divided by 2 (maximum) master bit frequency

•

Internal MCU clock (maximum) slave bit frequency

•

Four programmable master bit rates

•

Programmable clock polarity and phase

•

End of transmission interrupt flag

•

Write collision flag protection

•

Master-Master mode fault protection capability

14.1

SPI SIGNAL DESCRIPTION

The four basic signals (MOSI, MISO, SCK, SS) are described in the following paragraphs.

Each signal function is described for both the master and slave mode.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC05V7GRS/D Datasheet(PDF) 97 Page - NXP Semiconductors