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831742I Datasheet(PDF) 5 Page - Renesas Technology Corp

Part # 831742I
Description  4:2 Differential Clock/Data Multiplexer
PDF  21 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

831742I Datasheet(HTML) 5 Page - Renesas Technology Corp

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©2021 Renesas Electronics Corporation
R31DS0073EU0200 July 30, 2021
831742I Datasheet
AC Electrical Characteristics
Table 5A. PCI e Refclk Phase Jitter[1][2][3], VDD = 3.3V ± 0.3V, TA = -40°C to 85°C
1.
The Refclk jitter is measured after applying the filter functions found in PCI Express Base Specification 4.0, Revision 1.0. See the Test
Loads section of the data sheet for the exact measurement setup. The worst case results for each data rate are summarized in this table.
Equipment noise is removed from all measurements.
2.
Jitter measurements shall be made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a
sample rate of 20 GS/s or greater. Broadband oscilloscope noise must be minimized in the measurement. The measured PP jitter is used
(no extrapolation) for RTO measurements. Alternately - Jitter measurements may be used with a Phase Noise Analyzer (PNA) extending
(flat) and integrating and folding the frequency content up to an offset from the carrier frequency of at least 200 MHz (at 300 MHz absolute
frequency) below the Nyquist frequency. For PNA measurements for the 2.5 GT/s data rate, the RMS jitter is converted to peak-to-peak
jitter using a multiplication factor of 8.83.
3.
SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2 MHz taking care to minimize removal of any
non-SSC content.
4.
Note that 0.7 ps RMS is to be used in channel simulations to account for additional noise in a real system.
5.
The rms sum of the source jitter and the additive jitter (arithmetic sum for PCIe Gen1) must be less than the jitter specification listed.
Symbol
Parameter
Test Conditions
Minimum
Typical Maximum
Specification
Limit
Units
tjphPCIeG1-CC
Additive PCIe
Phase Jitter
(Common Clocked
Architecture)
PCIe Gen 1 (2.5 GT/s)
3.3
5
86 [5]
ps pk-pk
tjphPCIeG2-CC
PCIe Gen 2 Lo Band (5.0 GT/s)
54
61
3000 [5]
fs (RMS)
PCIe Gen 2 Hi Band (5.0 GT/s)
228
255
3100 [5]
tjphPCIeG3-CC
PCIe Gen 3 (8.0 GT/s)
116
130
1000 [5]
tjphPCIeG4-CC
PCIe Gen 4 (16.0 GT/s) [3] [4]
116
130
500 [5]



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