STM32H7B0IB datasheet(11/205 Pages) STMICROELECTRONICS

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Functional overview

3.1

Arm® Cortex®-M7 with FPU

The Arm® Cortex®-M7 with double-precision FPU processor is the latest generation of Arm processors

for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU

implementation, with a reduced pin count and optimized power consumption, while delivering outstanding

computational performance and low interrupt latency.

The Cortex®-M7 processor is a highly efficient high-performance featuring:

•

Six-stage dual-issue pipeline

•

Dynamic branch prediction

•

Harvard architecture with L1 caches (16 Kbytes of I-cache and 16 Kbytes of D-cache)

•

64-bit AXI4 interface

•

64-bit ITCM interface

•

2x32-bit DTCM interfaces

The following memory interfaces are supported:

•

Separate Instruction and Data buses (Harvard Architecture) to optimize CPU latency

•

Tightly Coupled Memory (TCM) interface designed for fast and deterministic SRAM accesses

•

AXI Bus interface to optimize Burst transfers

•

Dedicated low-latency AHB-Lite peripheral bus (AHBP) to connect to peripherals.

The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm

execution.

It also supports single and double precision FPU (floating point unit) speeds up software development by using

metalanguage development tools, while avoiding saturation.

Refer to Figure 1. STM32H7B0xB block diagram for the general block diagram of the STM32H7B0xB family.

Note:

Cortex®-M7 with FPU core is binary compatible with the Cortex®-M4 core.

3.2

Memory protection unit (MPU)

The memory protection unit (MPU) manages the CPU access rights and the attributes of the system resources.

It has to be programmed and enabled before use. Its main purposes are to prevent an untrusted user program

to accidentally corrupt data used by the OS and/or by a privileged task, but also to protect data processes or

read-protect memory regions.

The MPU defines access rules for privileged accesses and user program accesses. It allows defining up to 16

protected regions that can in turn be divided into up to 8 independent subregions, where region address, size, and

attributes can be configured. The protection area ranges from 32 bytes to 4 Gbytes of addressable memory.

When an unauthorized access is performed, a memory management exception is generated.

3.3

Memories

3.3.1

Embedded flash memory

The STM32H7B0xB devices embed up to 128 Kbytes of flash memory that can be used for storing programs and

data.

The flash memory is organized as 137-bit flash words memory that can be used for storing both code and data

constants. Each word consists of:

•

One flash word (4 words, 16 bytes or 128 bits)

•

9 ECC bits.

The Flash memory is organized as follows:

•

128 Kbytes of user Flash memory, containing 16 user sectors of 8 Kbytes each

•

128 Kbytes of System Flash memory from which the device can boot.

•

1 Kbyte of OTP (one-time programmable) memory containing option bytes for user configuration.

STM32H7B0xB

Functional overview

DS13196 - Rev 7

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