STM32H7B0IB datasheet(203/205 Pages) STMICROELECTRONICS

203 / 205 page

List of figures

Figure 1.

STM32H7B0xB block diagram ........................................................ 10

Figure 2.

Power-up/power-down sequence ...................................................... 14

Figure 3.

STM32H7B0xB bus matrix ........................................................... 18

Figure 4.

LQFP64 (STM32H7B0xB without SMPS) pinout ............................................ 35

Figure 5.

LQFP100 (STM32H7B0xB without SMPS) pinout ........................................... 36

Figure 6.

LQFP144 (STM32H7B0xB without SMPS) pinout ........................................... 37

Figure 7.

LQFP176 (STM32H7B0xB without SMPS) pinout ........................................... 38

Figure 8.

UFBGA169 (STM32H7B0xB with SMPS) ballout............................................ 39

Figure 9.

UFBGA176+25 (STM32H7B0xB with SMPS) ballout ......................................... 40

Figure 10.

Pin loading conditions .............................................................. 62

Figure 11.

Pin input voltage .................................................................. 62

Figure 12.

Power supply scheme .............................................................. 63

Figure 13.

Current consumption measurement scheme............................................... 64

Figure 14.

External capacitor CEXT ............................................................. 69

Figure 15.

SMPS efficicency vs load current in Run, Sleep and Stop mode with SVOS3 MR mode, TJ = 30 °C......... 71

Figure 16.

SMPS efficiency vs load current in Run, Sleep and Stop mode with SVOS3 MR mode, TJ = 130 °C ........ 71

Figure 17.

SMPS efficiency vs load current in Stop and DStop modes (SVOS3 LP mode, SVOS4, SVOS5), TJ = 30 °C .. 72

Figure 18.

SMPS efficiency vs load current in Stop and DStop modes (SVOS3 LP mode, SVOS4, SVOS5), TJ = 130 °C . 72

Figure 19.

SMPS efficiency vs load current in Stop and DStop2 modes (SVOS3 LP mode, SVOS4, SVOS5), TJ = 30 °C . 73

Figure 20.

SMPS efficiency vs load current in Stop and DStop2 modes (SVOS3 LP mode, SVOS4, SVOS5), TJ = 130 °C. 73

Figure 21.

High-speed external clock source AC timing diagram......................................... 90

Figure 22.

Low-speed external clock source AC timing diagram ......................................... 91

Figure 23.

Typical application with an 8 MHz crystal ................................................. 92

Figure 24.

Typical application with a 32.768 kHz crystal .............................................. 93

Figure 25.

VIL/VIH for all I/Os except BOOT0 ..................................................... 101

Figure 26.

Recommended NRST pin protection ................................................... 106

Figure 27.

Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms ............................ 107

Figure 28.

Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms ............................ 109

Figure 29.

Asynchronous multiplexed PSRAM/NOR read waveforms .....................................110

Figure 30.

Synchronous multiplexed NOR/PSRAM read timings.........................................113

Figure 31.

Synchronous multiplexed PSRAM write timings ............................................114

Figure 32.

Synchronous non-multiplexed NOR/PSRAM read timings .....................................116

Figure 33.

Synchronous non-multiplexed PSRAM write timings .........................................117

Figure 34.

NAND controller waveforms for read access...............................................118

Figure 35.

NAND controller waveforms for write access ..............................................119

Figure 36.

NAND controller waveforms for common memory read access ..................................119

Figure 37.

NAND controller waveforms for common memory write access ................................. 120

Figure 38.

SDRAM read access waveforms (CL = 1) ............................................... 121

Figure 39.

SDRAM write access waveforms ..................................................... 122

Figure 40.

OctoSPI timing diagram - SDR mode................................................... 125

Figure 41.

OctoSPI timing diagram - DTR mode................................................... 126

Figure 42.

OctoSPI Hyperbus clock ........................................................... 126

Figure 43.

OctoSPI Hyperbus read ............................................................ 126

Figure 44.

OctoSPI Hyperbus write............................................................ 127

Figure 45.

ADC conversion timing diagram ...................................................... 131

Figure 46.

ADC accuracy characteristics ........................................................ 132

Figure 47.

Typical connection diagram using the ADC with FT/TT pins featuring analog switch function............. 133

Figure 48.

Power supply and reference decoupling (VREF+ not connected to VDDA)........................... 134

Figure 49.

Power supply and reference decoupling (VREF+ connected to VDDA) ............................. 134

Figure 50.

12-bit buffered /non-buffered DAC..................................................... 137

Figure 51.

Channel transceiver timing diagrams ................................................... 145

Figure 52.

DCMI timing diagram.............................................................. 146

STM32H7B0xB

List of figures

DS13196 - Rev 7

page 203/205

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