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STM32H7B3AI Datasheet(PDF) 3 Page - STMicroelectronics |
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STM32H7B3AI Datasheet(HTML) 3 Page - STMicroelectronics |
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3 / 238 page  Graphics • LCD-TFT controller up to XGA resolution • Chrom-ART graphical hardware Accelerator (DMA2D) to reduce CPU load • Hardware JPEG Codec • Chrom-GRC™ (GFXMMU) Up to 19 timers and 2 watchdogs • 2× 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input (up to 280 MHz) • 2× 16-bit advanced motor control timers (up to 280 MHz) • 10× 16-bit general-purpose timers (up to 280 MHz) • 3× 16-bit low-power timers (up to 280 MHz) • 2× watchdogs (independent and window) • 1× SysTick timer • RTC with sub-second accuracy and hardware calendar Cryptographic acceleration • AES chaining modes: ECB,CBC,CTR,GCM,CCM for 128, 192 or 256 • HASH (MD5, SHA-1, SHA-2), HMAC • 2x OTFDEC AES-128 in CTR mode for Octo-SPI memory encryption/decryption • 1x 32-bit, NIST SP 800-90B compliant, true random generator Debug mode • SWD and JTAG interfaces • 4 KB Embedded Trace Buffer 96-bit unique ID All packages are ECOPACK2 compliant STM32H7B3xI DS13139 - Rev 8 page 3/238 |
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