IDT®

64-pin CK505 Compatible Clock w/Fully Integrated Voltage Regulator + Integrated Series Resistor

1533B—01/06/15

9LRS3165B

64-pin CK505 Compatible Clock w/Fully Integrated Voltage Regulator + Integrated Series Resistor

21

Byte 11 iAMT/CPU2 Control Register

Bit

Name

Description

Type

0

1

Default

7

Reserved

Reserved

RW

--

0

6

Reserved

Reserved

RW

--

0

5

Reserved

Reserved

RW

--

0

4

Reserved

Reserved

RW

--

0

3

CPU2_AMT_EN

M1 mode clk enable, only if ITP_EN=1

RW

Disable

Enable

0

2

CPU1_AMT_EN

M1 mode clk enable

RW

Disable

Enable

1

1

Reserved

Reserved

RW

--

0

0

CPU2 Stop Enable

Enables control of CPU2 with CPU_STOP#

RW

Free Running

Stoppable

1

Byte 12 Byte Count Register

Bit

Name

Description

Type

0

1

Default

7

Reserved

Reserved

RW

-

-

0

6

Reserved

Reserved

RW

-

-

0

5

BC5

RW

-

-

0

4

BC4

RW

-

-

0

3

BC3

RW

-

-

1

2

BC2

RW

-

-

1

1

BC1

RW

-

-

0

0

BC0

RW

-

-

1

Byte 13 Single Ended Output Slew Rate Control Register

Bit

Name

Description

RW

0

1

Default

7

REF

RW

00 = Hi-Z

01 = 1.4 V/ns

0

6

REF

RW

10 = 2.0 V/ns

11 = 2.4 V/ns

1

5

27M_FIX

RW

00 = Hi-Z

01 = 1.4 V/ns

0

4

27M_FIX

RW

10 = 2.0 V/ns

11 = 2.4 V/ns

1

3

27M_SS

RW

00 = Hi-Z

01 = 1.4 V/ns

0

2

27M_SS

RW

10 = 2.0 V/ns

11 = 2.4 V/ns

1

1

Reserved

Reserved

RW

-

-

0

0

Reserved

Reserved

RW

-

-

0

Byte 14 Reserved

Bit

Name

Description

Type

0

1

Default

7

Reserved

Reserved

RW

-

-

X

6

Reserved

Reserved

RW

-

-

X

5

Reserved

Reserved

RW

-

-

X

4

Reserved

Reserved

RW

-

-

X

3

Reserved

Reserved

RW

-

-

X

2

Reserved

Reserved

RW

-

-

X

1

Reserved

Reserved

RW

-

-

X

0

Reserved

Reserved

RW

-

-

X

Byte 15 Reserved

Bit

Name

Description

Type

0

1

Default

7

Reserved

Reserved

RW

-

-

X

6

Reserved

Reserved

RW

-

-

X

5

Reserved

Reserved

RW

-

-

X

4

Reserved

Reserved

RW

-

-

X

3

Reserved

Reserved

RW

-

-

X

2

Reserved

Reserved

RW

-

-

X

1

Reserved

Reserved

RW

-

-

X

0

Reserved

Reserved

RW

-

-

X

Byte 16 Reserved

Bit

Name

Description

Type

0

1

Default

7

Reserved

Reserved

RW

-

-

X

6

Reserved

Reserved

RW

-

-

X

5

Reserved

Reserved

RW

-

-

X

4

Reserved

Reserved

RW

-

-

X

3

Reserved

Reserved

RW

-

-

X

2

Reserved

Reserved

RW

-

-

X

1

Reserved

Reserved

RW

-

-

X

0

Reserved

Reserved

RW

-

-

X

Read Back byte count register,

max bytes = 32

Slew Rate Control

Slew Rate Control

Slew Rate Control