AT25QL128A datasheet(10/85 Pages) RENESAS

10 / 85 page

DS-AT25QL128A-129 Rev. G

Page 10

Nov 1, 2022

AT25QL128A Datasheet

HOLD

(I/O3)

HOLD

The HOLD pin is used to temporarily pause serial communication without deselecting

or resetting the device. While the HOLD pin is asserted, transitions on the SCK pin

and data on the SI pin are ignored, and the SO pin is placed in a high-impedance

state.

The CS pin must be asserted, and the SCK pin must be in the low state in order for a

Hold condition to start. A Hold condition pauses serial communication only and does

not have an effect on internally self-timed operations such as a program or erase

cycle.

With the Quad-Input Byte/Page Program command, the HOLD pin becomes an input

pin (I/O3) and with other pins, allows four bits (on I/O3-0) of data to be clocked in on

every rising edge of SCK. With the Quad-Output Read commands, the HOLD Pin

becomes an output pin (I/O3) in conjunction with other pins to allow four bits of data on

(I/O33-0) to be clocked in on every falling edge of SCK. To maintain consistency with

SPI nomenclature, the HOLD (I/O3) pin is referenced as the HOLD pin unless

specifically addressing the Quad-I/O modes, in which case it is referenced as I/O3.

The HOLD pin does not have an internal pull-up; thus, it must be either driven or, if not

used, pulled up with an external resistor to VCC. See Figure 1 and Figure 2 for the pin

configuration of Quad I/O and QPI operation.

–

Input/Output

VCC

DEVICE POWER SUPPLY:

VCC is the supply voltage. It is the single voltage used for all device functions,

including read, program, and erase. The VCC pin is used to supply the source voltage

to the device. Operations at invalid VCC voltages can produce spurious results; do

not attempt this.

–

Power

GND

GROUND:

VSS is the reference for the VCC supply voltage. The ground reference for the power

supply. Connect GND to the system ground.

–

Power

Table 1. Pin Descriptions (Continued)

Symbol

Name and Function

Asserted

State

Type

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