Figure 5. Typical application diagram for Vout < 1.25 V

Vi

INHIBIT

Isc

FILT C

GND

STAB

OCM

ADJ

Vo

RHFL6000L

OFF

ON

VIN

VOUT

IN+

Rload

Cin

Cfilt

Cout

R1

R2

Rsc

When VO < 1.25 V is required in the application, the divider resistor pair R2 and R1 are connected between

FILT_C, IN+ (middle point), and GND pins respectively, as shown in Figure 5. Typical application diagram for Vout

< 1.25 V and Figure 6. Detailed regulation loop diagram. VO is externally shorted to the ADJ/SENSE pin (as in

the typical control loop arranged in unity-gain feedback). Therefore, in this case, the output value (VO < 1.25 V) is

generated upstream to the error amplifier by fractioning the VBG value (available on FILT_C pin) according to the

ratio of the resistor divider composed by R1 and R2.

Figure 6. Detailed regulation loop diagram

+

_

Bandgap

loop

control

loop

VIN

VBG

2KΩ

R FILT_C

R2 ext

R1ext

C FILT_C

IR2ext

IIN+

VIN

VOUT

VREF

With reference to Figure 6. Detailed regulation loop diagram, the ideal scenario for the voltage at IN+, let us call it

VREF, is to get as close as possible to:

RHFL6000L

Typical application diagram

DS14125 - Rev 1

page 8/28