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Preliminary Technical Data

AD7693

Rev. PrB | Page 17 of 24

CS MODE 3-WIRE, NO BUSY INDICATOR

This mode is usually used when a single AD7693 is connected

to an SPI-compatible digital host. The connection diagram is

shown in Figure 33, and the corresponding timing is given in

Figure 34.

With SDI tied to VIO, a rising edge on CNV initiates a

conversion, selects the CS mode, and forces SDO to high

impedance. Once a conversion is initiated, it continues until

completion irrespective of the state of CNV. This could be

useful, for instance, to bring CNV low to select other SPI

devices, such as analog multiplexers; however, CNV must be

returned high before the minimum conversion time elapses and

then held high for the maximum possible conversion time to

avoid the generation of the busy signal indicator. When the

conversion is complete, the AD7693 enters the acquisition

phase and powers down. When CNV goes low, the MSB is

output onto SDO. The remaining data bits are clocked by

subsequent SCK falling edges. The data is valid on both SCK

edges. Although the rising edge can be used to capture the data,

a digital host using the SCK falling edge will allow a faster

reading rate, provided it has an acceptable hold time. After the

16th SCK falling edge, or when CNV goes high, whichever is

earlier, SDO returns to high impedance.

CNV

SCK

SDO

SDI

DATA IN

CLK

CONVERT

VIO

DIGITAL HOST

AD7693

Figure 33. 3-Wire

Mode Without Busy Indicator

Connection Diagram (SDI High)

SDO

D15

D14

D13

tDIS

SCK

tSCK

tSCKL

tSCKH

tHSDO

tDSDO

CNV

CONVERSION

ACQUISITION

tCONV

tCYC

ACQUISITION

SDI = 1

tCNVH

tACQ

tEN

Figure 34. 3-Wire

Mode Without Busy Indicator Serial Interface Timing (SDI High)

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