DS08MB200 datasheet(5/8 Pages) NSC

5 / 8 page

Electrical Characteristics (Continued)

Over recommended operating supply and temperature ranges unless other specified.

Symbol

Parameter

Conditions

Min

Typ

(Note 8)

Max

Units

SUPPLY CURRENT (Static)

Supply Current

All inputs and outputs enabled and

active, terminated with differential load

of 100

Ω between OUT+ and OUT-.

225

275

CCZ

Supply Current - Powerdown

Mode

ENA_0 = ENB_0 = ENL_0= ENA_1 =

ENB_1 = ENL_1 = L

0.6

4.0

SWITCHING CHARACTERISTICS — LVDS OUTPUTS

LHT

Differential Low to High Transition

Time

Use an alternating 1 and 0 pattern at

200 Mb/s, measure between 20% and

80% of V

OD. (Note 15)

170

250

HLT

Differential High to Low Transition

Time

170

250

PLHD

Differential Low to High

Propagation Delay

Use an alternating 1 and 0 pattern at

200 Mb/s, measure at 50% V

between input to output.

1.0

2.5

PHLD

Differential High to Low

Propagation Delay

1.0

2.5

SKD1

Pulse Skew

PLHD–tPHLD| (Note 15)

SKCC

Output Channel to Channel Skew

Difference in propagation delay (t

PLHD

or t

PHLD) among all output channels.

(Note 15)

115

JIT

Jitter

(Note 11)

RJ - Alternating 1 and 0 at 400 MHz

(Note 12)

1.3

1.5

psrms

DJ - K28.5 Pattern, 800 Mbps (Note 13)

psp-p

TJ - PRBS 2

7-1 Pattern, 800 Mbps

(Note 14)

psp-p

LVDS Output Enable Time

Time from ENA_n, ENB_n, or ENL_n to

OUT± change from TRI-STATE to

active.

0.5

1.5

µs

ON2

LVDS Output Enable time from

powerdown mode

Time from ENA_n, ENB_n, or ENL_n to

OUT± change from Powerdown to

active

µs

OFF

LVDS Output Disable Time

Time from ENA_n, ENB_n, or ENL_n to

OUT± change from active to

TRI-STATE or powerdown.

Note 8: Typical parameters are measured at VDD = 3.3V, TA = 25˚C. They are for reference purposes, and are not production-tested.

Note 9: Differential output voltage VOD is defined as ABS(OUT+–OUT−). Differential input voltage VID is defined as ABS(IN+–IN−).

Note 10: Output offset voltage VOS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.

Note 11: Jitter is not production tested, but guaranteed through characterization on a sample basis.

Note 12: Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = VID = 500mV, 50% duty cycle at 400

MHz, tr =tf = 50ps (20% to 80%).

Note 13: Deterministic Jitter, or DJ, is measured to a histogram mean with a sample size of 350 hits. Stimulus and fixture jitter has been subtracted. The input

voltage = VID = 500mV, K28.5 pattern at 800 Mbps, tr =tf = 50ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101).

Note 14: Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture jitter has been subtracted. The input voltage

=VID = 500mV, 2

7-1 PRBS pattern at 800 Mbps, t

r =tf = 50ps (20% to 80%).

Note 15: Not production tested. Guaranteed by statistical analysis on a sample basis at the time of characterization.

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