LOW VOLTAGE PLL CLOCK DRIVER

4

REVISION 7 3/14/16

MPC9351 DATA SHEET

Table 4. General Specifications

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

VTT

Output Termination Voltage

VCC 2

V

MM

ESD (Machine Model)

200

V

HBM

ESD (Human Body Model)

2000

V

LU

Latch-Up

200

mA

CPD

Power Dissipation Capacitance

10

pF

Per output

CIN

Input Capacitance

4.0

pF

Inputs

Table 5. DC Characteristics (VCC = 3.3 V  5%, TA = -40° to 85°C)

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

VIH

Input High Voltage

2.0

VCC + 0.3

V

LVCMOS

VIL

Input Low Voltage

0.8

V

LVCMOS

VPP

Peak-to-Peak Input Voltage PCLK, PCLK

250

mV

LVPECL

VCMR

(1)

1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range

and the input swing lies within the VPP (DC) specification.

Common Mode Range

PCLK, PCLK

1.0

VCC – 0.6

V

LVPECL

VOH

Output High Voltage

2.4

V

IOH = –24 mA

(2)

2. The MPC9351 is capable of driving 50

 transmission lines on the incident edge. Each output drives one 50  parallel terminated

transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50  series terminated transmission lines.

VOL

Output Low Voltage

0.55

0.30

V

V

IOL = 24 mA

IOL = 12 mA

ZOUT

Output Impedance

14 –17



IIN

Input Leakage Current

200

A

VIN = VCC or GND

ICCA

Maximum PLL Supply Current

3.0

5.0

mA

VCCA Pin

ICCQ

Maximum Quiescent Supply Current

1.0

mA

All VCC Pins

Table 6. AC Characteristics (VCC = 3.3 V  5%, TA = -40° to 85°C)

(1)

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

fref

Input Frequency

 2 feedback

 4 feedback

 8 feedback

Static test mode

100

50

25

0

200

100

50

300

MHz

MHz

MHz

MHz

PLL_EN = 1

PLL_EN = 1

PLL_EN = 1

PLL_EN = 0

fVCO

VCO Frequency

200

400

MHz

fMAX

Maximum Output Frequency

 2 output

 4 output

 8 output

100

50

25

200

100

50

MHz

MHz

MHz

frefDC

Reference Input Duty Cycle

25

75

%

VPP

Peak-to-Peak Input Voltage PCLK, PCLK

500

1000

mV

LVPECL

VCMR

(2)

Common Mode Range

PCLK, PCLK

1.2

VCC – 0.9

V

LVPECL

tr, tf

TCLK Input Rise/Fall Time

1.0

ns

0.8 to 2.0V

t()

Propagation Delay (static phase offset)

TCLK to EXT_FB

PCLK to EXT_FB

–50

+25

+150

+325

ps

ps

PLL locked

PLL locked