MPC93R51

REVISION 4 MARCH 14, 2016

2

©2013 Integrated Device Technology, Inc.

MPC93R51 Data Sheet

LOW VOLTAGE PLL CLOCK DRIVER

Figure 1. MPC93R51 Logic Diagram

Figure 2. Pinout: 32-Lead Package Pinout (Top View)

D

Q

PLL

(Pulldown)

EXT_FB

FSELA

QA

REF_SEL

0

1

(Pullup)

Ref

FB

200 – 480 MHz



2



4



8

QB

0

1

0

1

0

1

FSELB

FSELC

(Pulldown)

(Pulldown)

(Pullup)

(Pulldown)

PLL_EN

FSELD

D

Q

QC1

0

1

D

Q

QC0

QD2

0

1

D

Q

QD1

QD0

QD4

QD3

(Pulldown)

(Pulldown)

(Pulldown)

(Pulldown)

TCLK

PCLK

OE

PCLK

The MPC93R51 requires an external RC filter for the analog power supply pin VCCA. Please see Applications Information for details.

GND

QB

VCCO

QA

GND

TCLK

PLL_EN

QD2

VCCO

QD3

GND

QD4

VCCO

25

26

27

28

29

30

31

32

15

14

13

12

11

10

9

1234

5

67

8

24

23

22

21

20

19

18

17

16

MPC93R51

REF_SEL

OE

PCLK