DATASHEET

Intelligent Dynamic Clock Switch (IDCS)

PLL Clock Driver

MPC9993

MPC9993 REVISION 3 JANUARY 23, 2013

1

©2013 Integrated Device Technology, Inc.

The MPC9993 is a PLL clock driver designed specifically for redundant clock

tree designs. The device receives two differential LVPECL clock signals from

which it generates 5 new differential LVPECL clock outputs. Two of the output

pairs regenerate the input signals frequency and phase while the other three

pairs generate 2x, phase aligned clock outputs.

Features

•

Fully Integrated PLL

•

Intelligent Dynamic Clock Switch

•

LVPECL Clock Outputs

•

LVCMOS Control I/O

•

3.3 V Operation

•

32-Lead LQFP Packaging

•

32-Lead Pb-Free Package Available

Functional Description

The MPC9993 Intelligent Dynamic Clock Switch (IDCS) circuit continuously

monitors both input CLK signals. Upon detection of a failure (CLK stuck HIGH or

LOW for at least 1 period), the INP_BAD for that CLK will be latched (H). If that

CLK is the primary clock, the IDCS will switch to the good secondary clock and

phase/frequency alignment will occur with minimal output phase disturbance.

The typical phase bump caused by a failed clock is eliminated. (See Application

Information section).

FA SUFFIX

32-LEAD LQFP PACKAGE

CASE 873A-04

AC SUFFIX

32-LEAD LQFP PACKAGE

Pb-FREE PACKAGE

CASE 873A-04

MPC9993

INTELLIGENT DYNAMIC

CLOCK SWITCH

PLL CLOCK DRIVER

CLK0

CLK0

CLK1

CLK1

Ext_FB

Ext_FB

Sel_Clk

Dynamic

Switch

Logic

PLL

PLL_En

8

16

Qb0

Qb0

Qb1

Qb1

Qb2

Qb2

Qa0

Qa0

Qa1

Qa1

MR

Man_Override

Clk_Selected

Inp1bad

Inp0bad

Alarm_Reset

800 – 1600 MHz

OR

Figure 1. Block Diagram

Product Discontinuance Notice – Last Time Buy Expires on (12/7/2013)