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L6382D

Table 2. Pin Functions

N.

Pin

Function

1

PFI

Digital input signal to control the PFC gate driver. This pin has to be connected to a TTL

compatible signal.

2

LSI

Digital input signal to control the half-bridge low side driver. This pin has to be connected to a

TTL compatible signal.

3

HSI

Digital input signal to control the half-bridge high side driver. This pin has to be connected to a

TTL compatible signal.

4

HEI

Digital input signal to control the HEG output. This pin has to be connected to a TTL compatible

signal.

5

PFG

PFC Driver Output. This pin must be connected to the PFC power MOSFET gate. A resistor

connected between this pin and the power MOS gate can be used to reduce the peak current.

An internal 10K

Ω resistor toward ground avoids spurious and undesired MOSFET turn-on

The totem pole output stage is able to drive the power MOS with a peak current of 120mA

source and 250mA sink.

6

N.C.

Not connected

7

TPR

Input for two point regulator; by coupling the pin with a capacitor to a switching circuit, it is

possible to implement a charge circuit for the Vcc.

8

GND

Chip ground. Current return for both the low-side gate-drive currents and the bias current of the

IC. All of the ground connections of the bias components should be tied to a track going to this

pin and kept separate from any pulsed current return.

9

LSG

Low Side Driver Output. This pin must be connected to the gate of the half-bridge low side

power MOSFET. A resistor connected between this pin and the power MOS gate can be used

to reduce the peak current.

An internal 20K

Ω resistor toward ground avoids spurious and undesired MOSFET turn-on.

The totem pole output stage is able to drive power with a peak current of 120mA source and

120mA sink.

10

Vcc

Supply Voltage for the signal part of the IC and for the drivers.

11

BOOT

High-side gate-drive floating supply Voltage. The bootstrap capacitor connected between this

pin and pin 13 (OUT) is fed by an internal synchronous bootstrap diode driven in phase with the

low-side gate-drive. This patented structure normally replaces the external diode.

12

HSG

High Side Driver Output. This pin must be connected to the gate of the half bridge high side

power MOSFET . A resistor connected between this pin and the power MOS gate can be used

to reduce the peak current.

An internal 20K

Ω resistor toward OUT pin avoids spurious and undesired MOSFET turn-on

The totem pole output stage is able to drive the power MOS with a peak current of 120mA

source and 120mA sink.

13

OUT

High-side gate-drive floating ground. Current return for the high-side gate-drive current. Layout

carefully the connection of this pin to avoid too large spikes below ground.

14

N.C.

Not connected

15

HVSU

High-voltage start-up. The current flowing into this pin charges the capacitor connected

between pin Vcc and GND to start up the IC. Whilst the chip is in save mode, the generator is

cycled on-off between turn-on and

mode the generator is shut down and it is re-enabled when the Vcc voltage falls below the

rectified mains voltage either directly or through a resistor.

16

N.C.

High-voltage spacer. The pin is not connected internally to isolate the high-voltage pin and

comply with safety regulations (creepage distance) on the PCB.

17

HEG

Output for the HEI block; this driver can be used to drive the MOS employed in isolated

filaments preheating. An internal 20K

Ω resistor toward ground avoids spurious and undesired

MOSFET turn-on.