3

Integrated

Circuit

Systems, Inc.

ICS9DB104

(Not recommended for new designs)

0767E—12/14/07

ICS9DB104 follows the Intel DB400 Differential Buffer Specification. This buffer provides four SRC clocks for PCI-Express,

next generation I/O devices. ICS9DB104 is driven by a differential input pair from a CK409/CK410 main clock generator, such

as the ICS952601 or ICS954101. ICS9DB104 can run at speeds up to 200MHz. It provides ouputs meeting tight cycle-to-cycle

jitter (50ps) and output-to-output skew (50ps) requirements.

General Description

Block Diagram

Power Groups

STOP

LOGIC

SRC_IN

SRC_IN#

DIF(1,2,5,6)

CONTROL

LOGIC

HIGH_BW#

BYPASS#/PLL

SDATA

SCLK

SRC_STOP#

PD#

SPREAD

COMPATIBLE

PLL

4

IREF

OE1, OE6

2

VDD

GND

1

4

SRC_IN/SRC_IN#

5,11,18,24

4,25

DIF Outputs

28

27

IREF

28

27

Analog VDD & GND for PLL core

Description

Pin Number