9

ICS9LPRS355

Datasheet

1205—06/24/14

MLF Pin Description (Continued)

PIN #

PIN NAME

TYPE

DESCRIPTION

33

VDDSRC_IO

PWR

1.05V to 3.3V from external power supply

34

SRCT4

I/O

True clock of differential SRC clock pair 4

35

SRCC4

I/O

Complement clock of differential SRC clock pair 4

36

GNDSRC

PWR

Ground pin for SRC clocks.

37

SRCT9

OUT

True clock of differential SRC clock pair.

38

SRCC9

OUT

Complement clock of differential SRC clock pair.

39

SRCC11/CR#_G

I/O

SRC11 complement /Clock Request control for SRC9 pair

The power-up default is SRC11#, but this pin may also be used as a Clock Request control of

SRC9 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair

must first be disabled in byte 3, bit 7 of SMBus configuration space After the SRC11 output is

disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC9 pair using byte

6, bit 5 of SMBus configuration space

Byte 6, bit 5

0 = SRC11# enabled (default)

1= CR#_G controls SRC9

40

SRCT11/CR#_H

I/O

SRC11 true or Clock Request control H for SRC10 pair

The power-up default is SRC11, but this pin may also be used as a Clock Request control of

SRC10 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair

must first be disabled in byte 3, bit 7 of SMBus configuration space After the SRC11 output is

disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC10 pair using

byte 6, bit 4 of SMBus configuration space

Byte 6, bit 4

0 = SRC11 enabled (default)

1= CR#_H controls SRC10.

41

SRCT10

OUT

True clock of differential SRC clock pair.

42

SRCC10

OUT

Complement clock of differential SRC clock pair.

43

VDDSRC_IO

PWR

1.05V to 3.3V from external power supply

44

CPU_STOP#

IN

Stops all CPU Clocks, except those set to be free running clocks. In AMT mode 3 bits are

shifted in from the ICH to set the FSC, FSB, FSA values

45

PCI_STOP#

IN

Stops all PCI Clocks, except those set to be free running clocks. In AMT mode 3 bits are shifted

in from the ICH to set the FSC, FSB, FSA values

46

VDDSRC

PWR

VDD pin for SRC Pre-drivers, 3.3V nominal

47

SRCC6

OUT

Complement clock of low power differential SRC clock pair.

48

SRCT6

OUT

True clock of low power differential SRC clock pair.