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ICS9LPRS502 Datasheet(PDF) 1 Page - Renesas Technology Corp |
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ICS9LPRS502 Datasheet(HTML) 1 Page - Renesas Technology Corp |
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1 / 30 page  ICS9LPRS502 IDTTM/ICSTM 56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1125E—02/26/09 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR 1 Datasheet Recommended Application: Key Specifications: CK505 compliant clock with fully integrated voltage regulator and Internal series resistor on differential outputs, PCIe Gen 1 compliant • CPU outputs cycle-cycle jitter < 85ps • SRC output cycle-cycle jitter < 125ps • PCI outputs cycle-cycle jitter < 250ps • +/- 100ppm frequency accuracy on CPU & SRC clocks Pin Configuration Output Features: • 2 - CPU differential low power push-pull pairs • 7 - SRC differential low power push-pull pairs • 1 - CPU/SRC selectable differential low power push-pull pair • 1 - SRC/DOT selectable differential low power push-pull pair • 5 - PCI, 33MHz • 1 - PCI_F, 33MHz free running • 1 - USB, 48MHz • 1 - REF, 14.318MHz Features/Benefits: • Does not require external pass transistor for voltage regulator • Integrated series resistors on differential outputs, Zo=50W • Supports spread spectrum modulation, default is 0.5% down spread • Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning • One differential push-pull pair selectable between SRC and two single-ended outputs Table 1: CPU Frequency Select Table PCICLK0/CR#_A 1 56 SCLK VDDPCI 2 55 SDATA PCICLK1/CR#_B 3 54 FSLC/TEST_SEL/REF0 PCICLK2/LTE 4 53 VDDREF PCICLK3 5 52 X1 PCICLK4/SRC5_EN 6 51 X2 PCI_F5/ITP_EN 7 50 GNDREF GNDPCI 8 49 FSLB/TEST_MODE VDD48 9 48 CK_PWRGD/PD# USB_48MHz/FSLA 10 47 VDDCPU GND48 11 46 CPUCLKT0 VDD96I/O 12 45 CPUCLKC0 DOTT_96/SRCCLKT0 13 44 GNDCPU DOTC_96/SRCCLKC0 14 43 CPUCLKT1 GND 15 42 CPUCLKC1 VDD 16 41 VDDCPUI/O SRCCLKT1/SE1 17 40 NC SRCCLKC1/SE2 18 39 CPUCLKT2_ITP/SRCCLKT8 GND 19 38 CPUCLKC2_ITP/SRCCLKC8 VDDPLL3I/O 20 37 VDDSRCI/O SRCCLKT2/SATACLKT 21 36 SRCCLKT7/CR#_F SRCCLKC2/SATACLKC 22 35 SRCCLKC7/CR#_E GNDSRC 23 34 GNDSRC SRCCLKT3/CR#_C 24 33 SRCCLKT6 SRCCLKC3/CR#_D 25 32 SRCCLKC6 VDDSRCI/O 26 31 VDDSRC SRCCLKT4 27 30 PCI_STOP#/SRCCLKT5 SRCCLKC4 28 29 CPU_STOP#/SRCCLKC5 56-SSOP/TSSOP * Internal Pull-Up Resistor ** Internal Pull-Down Resistor FSLC 2 B0b7 FSLB 1 B0b6 FSLA 1 B0b5 CPU MHz SRC MHz PCI MHz REF MHz USB MHz DOT MHz 0 0 0 266.66 0 0 1 133.33 0 1 0 200.00 0 1 1 166.66 1 0 0 333.33 1 0 1 100.00 1 1 0 400.00 11 1 1. FS LA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FS LC is a three-level input. Please see the VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Reserved 100.00 33.33 14.318 48.00 96.00 |
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