 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ICS9LPRS535 Datasheet(PDF) 11 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
ICS9LPRS535 Datasheet(HTML) 11 Page - Renesas Technology Corp |
|
|
11 / 18 page  11 Integrated Circuit Systems, Inc. ICS9LPRS535 Datasheet 1461A—07/28/09 Byte 0 FS Readback and PLL Selection Register Bit Pin Name Description Type 0 1 Default 7 - FSLC CPU Freq. Sel. Bit (Most Significant) R Latch 6 - FSLB CPU Freq. Sel. Bit R Latch 5 - FSLA CPU Freq. Sel. Bit (Least Significant) R Latch 4- iAMT_EN Set via SMBus or dynamically by CK505 if detects dynamic M1 RW Legacy Mode iAMT Enabled 0 3 Reserved Reserved RW 0 2 - SRC_Main_SEL Select source for SRC Main R SRC Main = PLL1 SRC Main = PLL3 0 1 - SATA_SEL Select source for SATA clock RW SATA = SRC_Main SATA = PLL2 0 0 - PD_Restore 1 = on Power Down de-assert return to last known state 0 = clear all SMBus configurations as if cold power-on and go to latches open state This bit is ignored and treated at '1' if device is in iAMT mode. RW Configuration Not Saved Configuration Saved 1 Byte 1 DOT96 Select and PLL3 Quick Config Register Bit Pin Name Description Type 0 1 Default 7 13/14 SRC0_SEL Select SRC0 or DOT96 RW SRC0 DOT96 0 6 - PLL1_SSC_SEL Select 0.5% down or center SSC RW Down spread Center spread 0 5 Reserved Reserved RW 1 4 PLL3_CF3 PLL3 Quick Config Bit 3 R 1 3 PLL3_CF2 PLL3 Quick Config Bit 2 R 1 2 PLL3_CF1 PLL3 Quick Config Bit 1 R 0 1 PLL3_CF0 PLL3 Quick Config Bit 0 R 0 0 PCI_SEL PCI_SEL R PCI from PLL1 PCI from SRC_MAIN 1 Byte 2 Output Enable Register Bit Pin Name Description Type 0 1 Default 7 REF_OE Output enable for REF, if disabled output is tri-stated RW Output Disabled Output Enabled 1 6 USB_OE Output enable for USB RW Output Disabled Output Enabled 1 5 PCIF5_OE Output enable for PCI5 RW Output Disabled Output Enabled 1 4 PCI4_OE Output enable for PCI4 RW Output Disabled Output Enabled 1 3 Reserved Reserved RW 1 2 Reserved Reserved RW 1 1 Reserved Reserved RW 1 0 PCI0_OE Output enable for PCI0 RW Output Disabled Output Enabled 1 Byte 3 Output Enable Register Bit Pin Name Description Type 0 1 Default 7 Reserved Reserved RW 1 6 Reserved Reserved RW 1 5 Reserved Reserved RW 1 4 SRC8/ITP_OE Output enable for SRC8 or ITP RW Output Disabled Output Enabled 1 3 SRC7_OE Output enable for SRC7 RW Output Disabled Output Enabled 1 2 Reserved Reserved RW 1 1 SRC5_OE Output enable for SRC5 RW Output Disabled Output Enabled 1 0 SRC4_OE Output enable for SRC4 RW Output Disabled Output Enabled 1 See Table 1 : CPU Frequency Select Table 25MHz from PLL3 Quick Config |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
British ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
