ICS853S031I Data Sheet

LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

ICS853S031BYI REVISION A AUGUST 17, 2011

2

©2011 Integrated Device Technology, Inc.

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number

Name

Type

Description

1VCC

Power

Positive supply pin.

2

CLK

Input

Pulldown

Non-inverting differential clock input.

3

nCLK

Input

Pullup

Inverting differential clock input.

4

CLK_SEL

Input

Pulldown

Clock select input. When HIGH, selects PCLK/nPCLK inputs. When LOW, selects

CLK/nCLK inputs. LVTTL / LVCMOS interface levels.

5

PCLK

Input

Pulldown

Non-inverting differential LVPECL clock input.

6

nPCLK

Input

Pullup

Inverting differential LVPECL clock input.

7VEE

Power

Negative supply pin.

8

CLK_EN

Input

Pullup

Synchronizing clock enable. When HIGH, clock outputs follow clock input. When

LOW, Qx outputs are forced low, nQx outputs are forced high. LVTTL/LVCMOS

interface levels.

9, 16, 17,

24, 25, 32

VCCO

Power

Output supply pins.

10, 11

nQ8, Q8

Output

Differential output pair. LVPECL/ECL interface levels.

12, 13

nQ7, Q7

Output

Differential output pair. LVPECL/ECL interface levels.

14, 15

nQ6, Q6

Output

Differential output pair. LVPECL/ECL interface levels.

18, 19

nQ5, Q5

Output

Differential output pair. LVPECL/ECL interface levels.

20, 21

nQ4, Q4

Output

Differential output pair. LVPECL/ECL interface levels.

22, 23

nQ3, Q3

Output

Differential output pair. LVPECL/ECL interface levels.

26, 27

nQ2, Q2

Output

Differential output pair. LVPECL/ECL interface levels.

28, 29

nQ1, Q1

Output

Differential output pair. LVPECL/ECL interface levels.

30, 31

nQ0, Q0

Output

Differential output pair. LVPECL/ECL interface levels.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

RPULLDOWN

Input Pulldown Resistor

50

k

Ω

RPULLUP

Input Pullup Resistor

50

k

Ω