DSM2180F3V datasheet(37/63 Pages) STMICROELECTRONICS

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DSM2180F3V

Figure 22. Port D Structure

Port D – Functionality and Structure

Port D has three I/O pins. See Figure 22 and Fig-

ure 23. Port D can be configured to perform one or

more of the following functions:

MCU I/O Mode

DPLD Output – External Chip Selects, ECS0-2

does not consume OMCs

CPLD Input – direct input to the CPLD, does not

use IMCs

Slew rate – pins can be set up for fast slew rate

Port D pins can be configured in PSDsoft as in-

put pins for other dedicated functions:

CLKIN (PD1) as input to the OMCs Flip-flops

PSD Chip Select Input (CSI, PD2). Driving this

signal logic High disables the Flash memory,

putting it in standby mode.

External Chip Select. The DPLD also provides

three External Chip Select outputs (ESC0-2) on

Port D pins that can be used to select external de-

vices as defined in PSDsoft Express. Each Exter-

nal Chip Select consists of one product term that

can be configured active High or Low. The output

enable of the pin is controlled by either the output

enable product term or the Direction Register.

(See Figure 23.) External Chip Selects for Port D

pins do not consume OMCs. External chip select

outputs can also come from the CPLD if chip se-

lect equations are specified in PSDsoft Express for

Ports B or C.

DATA OUT

REG.

ECS[ 2: 0]

READ MUX

CPLD - INPUT

DIR REG.

DATA IN

ENABLE PRODUCT

TERM (.OE)

OUTPUT

SELECT

OUTPUT

MUX

PORT D PIN

DATA OUT

AI02889

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