PCF5270AB100 datasheet(4/56 Pages) FREESCALE

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MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2

Features

Freescale Semiconductor

3Features

This document contains information on a new product. Specifications and information herein are subject

to change without notice.

3.1

Feature Overview

•

Version 2 ColdFire variable-length RISC processor core

— Static operation

— 32-bit address and data path on-chip

— Processor core runs at twice the bus frequency

— Sixteen general-purpose 32-bit data and address registers

— Implements the ColdFire Instruction Set Architecture, ISA_A, with extensions to support the

user stack pointer register, and 4 new instructions for improved bit processing

— Enhanced Multiply-Accumulate (EMAC) unit with four 48-bit accumulators to support 32-bit

signal processing algorithms

— Illegal instruction decode that allows for 68K emulation support

•

System debug support

— Real time trace for determining dynamic execution path

— Background debug mode (BDM) for in-circuit debugging

— Real time debug support, with two user-visible hardware breakpoint registers (PC and address

with optional data) that can be configured into a 1- or 2-level trigger

•

On-chip memories

— 8-Kbyte cache, configurable as instruction-only, data-only, or split I-/D-cache

— 64-Kbyte dual-ported SRAM on CPU internal bus, accessible by core and non-core bus

masters (e.g., DMA, FEC)

•

Fast Ethernet Controller (FEC)

— 10 BaseT capability, half duplex or full duplex

— 100 BaseT capability, half duplex or full duplex

— On-chip transmit and receive FIFOs

— Built-in dedicated DMA controller

— Memory-based flexible descriptor rings

— Media independent interface (MII) to external transceiver (PHY)

•

Three Universal Asynchronous Receiver Transmitters (UARTs)

— 16-bit divider for clock generation

— Interrupt control logic

— Maskable interrupts

— DMA support

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