S71GS256 datasheet(5/195 Pages) SPANSION

5 / 195 page

December 17, 2004 S71GS256/128N_00_A0

Ad vance

Info rmat i o n

Table 44. Asynchronous WRITE Timing

Parameters—CE#-Controlled .............................................147

Figure 49. LB#/UB#-Controlled Asynchronous WRITE ........... 149

Table 45. Asynchronous WRITE Timing Parameters—LB#/UB#-

Controlled .......................................................................149

Figure 50. WE#-Controlled Asynchronous WRITE.................. 151

Table 46. Asynchronous WRITE Timing Parameters—WE#-

Controlled .......................................................................151

Figure 51. Asynchronous WRITE Using ADV#....................... 153

Table 47. Asynchronous WRITE Timing

Parameters Using ADV# ....................................................154

Figure 52. Burst WRITE Operation ...................................... 155

Table 48. Burst WRITE Timing Parameters ...........................156

Figure 53. Continuous Burst WRITE Showing an Output Delay with

BCR[8] = 0 for End-of-Row Condition ................................. 157

Table 49. Burst WRITE Timing Parameters—BCR[8] = 0 ........157

Figure 54. Burst WRITE Followed by Burst READ .................. 158

Table 50. WRITE Timing Parameters—Burst WRITE Followed by

Burst READ .....................................................................158

Table 51. READ Timing Parameters—Burst WRITE Followed by Burst

READ ..............................................................................158

Figure 55. Asynchronous WRITE Followed by Burst READ ...... 159

Table 52. WRITE Timing Parameters—Asynchronous WRITE

Followed by Burst READ ....................................................160

Table 53. READ Timing Parameters—Asynchronous WRITE Followed

by Burst READ .................................................................160

Figure 56. Asynchronous WRITE (ADV# LOW) Followed By Burst

READ.............................................................................. 161

Table 54. Asynchronous WRITE Timing

Parameters—ADV# LOW ...................................................161

Table 55. Burst READ Timing Parameters ............................162

Figure 57. Burst READ Followed by Asynchronous WRITE (WE#-Con-

trolled) ........................................................................... 163

Table 56. Burst READ Timing Parameters ............................164

Table 57. Asynchronous WRITE Timing

Parameters—WE# Controlled .............................................164

Figure 58. Burst READ Followed by Asynchronous WRITE Using

ADV# ............................................................................. 165

Table 58. Burst READ Timing Parameters ............................166

Table 59. Asynchronous WRITE Timing

Parameters Using ADV# ....................................................166

Figure 59. Asynchronous WRITE Followed by Asynchronous READ—

ADV# LOW...................................................................... 167

Table 60. WRITE Timing Parameters—ADV# LOW .................167

Table 61. READ Timing Parameters—ADV# LOW ..................168

Figure 60. Asynchronous WRITE Followed by

Asynchronous READ ......................................................... 169

Table 62. WRITE Timing Parameters—Asynchronous WRITE

Followed by Asynchronous READ ........................................169

Table 63. READ Timing Parameters—Asynchronous WRITE Followed

by Asynchronous READ .....................................................170

How Extended Timings Impact CellularRAM™

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Introduction ........................................................................................................170

Asynchronous WRITE Operation ................................................................ 171

Figure 61. Extended Timing for tCEM.............................................. 171

Figure 62. Extended Timing for tTM................................................ 171

Table 64. Extended Cycle Impact on READ and WRITE Cycles 171

Extended WRITE Timing— Asynchronous WRITE Operation ...... 171

Figure 63. Extended WRITE Operation ................................ 172

Page Mode READ Operation ........................................................................ 172

Burst-Mode Operation .................................................................................... 172

Summary .............................................................................................................. 172

CellularRAM-2A

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

General Description . . . . . . . . . . . . . . . . . . . . . . 173

Figure 64. Functional Block Diagram................................... 174

Table 65. Pin Descriptions ................................................. 174

Table 66. Bus Operations—Asynchronous Mode ................... 175

Functional Description . . . . . . . . . . . . . . . . . . . . .176

Power-Up Initialization ....................................................................................176

Figure 65. Power-Up Initialization Timing ............................ 176

Bus Operating Modes . . . . . . . . . . . . . . . . . . . . . 176

Asynchronous Mode ........................................................................................176

Figure 66. READ Operation................................................ 177

Figure 67. WRITE Operation .............................................. 177

Page Mode READ Operation ........................................................................ 177

Figure 68. Page Mode READ Operation................................ 178

LB# / UB# Operation ......................................................................................178

Low Power Operation . . . . . . . . . . . . . . . . . . . . . 178

Standby Mode Operation ...............................................................................178

Temperature Compensated Refresh ...........................................................178

Partial Array Refresh ........................................................................................179

Deep Power-Down Operation .....................................................................179

Configuration Register Operation ...............................................................179

Figure 69. Load Configuration Register Operation................. 180

Table 67. Configuration Register Bit Mapping ....................... 181

Table 68. 64Mb Address Patterns for PAR (CR[4] = 1) .......... 181

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 182

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 183

Table 69. Electrical Characteristics and Operating Conditions . 183

Table 70. Temperature Compensated Refresh Specifications and

Conditions ....................................................................... 183

Table 71. Partial Array Refresh Specifications and Conditions . 184

Table 72. Deep Power-Down Specifications .......................... 184

Table 73. Capacitance Specifications and Conditions ............. 184

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 184

Figure 70. AC Input/Output Reference Waveform................. 184

Figure 71. Output Load Circuit........................................... 184

Table 74. Output Load Circuit ............................................ 184

Table 75. READ Cycle Timing Requirements ......................... 185

Table 76. WRITE Cycle Timing Requirements ....................... 186

Table 77. Load Configuration Register Timing Requirements .. 186

Table 78. Deep Power Down Timing Requirements ............... 186

Table 79. Power-up Initialization Timing Parameters ............. 187

Figure 72. Power-up Initialization Period ............................. 187

Figure 73. Load Configuration Register Timing ..................... 187

Table 80. Load Configuration Register Timing Requirements .. 187

Figure 74. Deep Power Down Entry/Exit TIming................... 188

Table 81. Load Configuration Register Timing Requirements .. 188

Figure 75. Single READ Operation (WE# = VIH) ................... 188

Table 82. READ Timing Parameters .................................... 189

Figure 76. Page Mode Read Operation (WE# = VIH) ............. 189

Table 83. Page Mode READ Timing Parameters .................... 189

Figure 77. WRITE Cycle (WE# Control) ............................... 190

Table 84. Write Timing Parameters ..................................... 190

Figure 78. Write Timing Parameters (CE# Control)............... 191

Table 85. Write Timing Parameters (CE# Control) ................ 191

Figure 79. WRITE Cycle (LB# / UB# Control)....................... 192

Table 86. Write Timing Parameters (LB# / UB# Control) ....... 192

How Extended Timings Impact CellularRAM™

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Introduction ........................................................................................................193

Operation When Page Mode is Disabled ..................................................193

Figure 80. Extended Timing for tCEM.............................................. 193

Figure 81. Extended Timing for tTM................................................ 193

Operation When Page Mode is Enabled ....................................................193

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