ICS87004AG REVISION C DECEMBER 1, 2009

10

©2009 Integrated Device Technology, Inc.

ICS87004 Data Sheet

1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR

Application Information

Power Supply Filtering Technique

As in any high speed analog circuitry, the power supply pins are

vulnerable to random noise. To achieve optimum jitter performance,

power supply isolation is required. The ICS87004 provides separate

power supplies to isolate any high switching noise from the outputs

to the internal PLL. VDD, VDDA and VDDO should be individually

connected to the power supply plane through vias, and 0.01µF

bypass capacitors should be used for each pin. Figure 1 illustrates

this for a generic VDD pin and also shows that VDDA requires that an

additional 10

Ω resistor along with a 10µF bypass capacitor be

connected to the VDDA pin. The 10Ω resistor can also be replaced by

a ferrite bead.

Figure 1. Power Supply Filtering

Wiring the Differential Input to Accept Single Ended Levels

Figure 2 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = VDD/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio of

R1 and R2 might need to be adjusted to position the V_REF in the

center of the input voltage swing. For example, if the input clock swing

is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 =

0.609.

Figure 2. Single-Ended Signal Driving Differential Input

Recommendations for Unused Input and Output Pins

Inputs:

CLK/nCLK Inputs

For applications not requiring the use of the differential input, both

CLK and nCLK can be left floating. Though not required, but for

additional protection, a 1k

Ω resistor can be tied from CLK to ground.

LVCMOS Control Pins

All control pins have internal pullups or pulldowns; additional

resistance is not required but can be added for additional protection.

A 1k

Ω resistor can be used.

Outputs:

LVCMOS Outputs

All unused LVCMOS output can be left floating. There should be no

trace attached.

VDD

VDDA

3.3V or 2.5V

10

Ω

10µF

.01µF

.01µF

V_REF

Single Ended Clock Input

VDD

CLKx

nCLKx

R1

1K

C1

0.1u

R2

1K