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ICS93701 Datasheet(PDF) 3 Page - Renesas Technology Corp

Part # ICS93701
Description  DDR Phase Lock Loop Clock Driver
PDF  9 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ICS93701 Datasheet(HTML) 3 Page - Renesas Technology Corp

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Byte 0: OutputControl
(1=
enable, 0= disable)
BIT
PIN# PWD
Bit 7
3,2
1
Bit 6
5,6
1
Bit 5
10,9
1
Bit 4
20,19
1
Bit 3
22,23
1
Bit 2
46,47
1
Bit 1
44,43
1
Bit 0
39,40
1
Byte2: Reserved
(1=
enable, 0= disable)
BIT
PIN# PWD
Bit 7
-
1
Bit 6
-
1
Bit 5
-
1
Bit 4
-
1
Bit 3
-
1
Bit 2
-
1
Bit 1
-
1
Bit 0
-
1
Byte4: Reserved
(1=
enable, 0= disable)
BIT
PIN#
PWD
Bit 7
-
1
Bit 6
-
1
Bit 5
-
1
Bit 4
-
1
Bit 3
-
1
Bit 2
-
1
Bit 1
-
1
Bit 0
-
1
0417B---10/29/02
DESCRIPTION
CLKT0,CLKC0
CLKT1,CLKC1
CLKT2,CLKC2
CLKT3,CLKC3
CLKT4,CLKC4
CLKTS,CLKCS
CLKT6,CLKC6
CLKT7,CLKC7
DESCRIPTION
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DESCRIPTION
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
3
ICS93701
Byte 1: OutputControl
(1=
enable, 0= disable)
BIT
PIN# PWD
DESCRIPTION
Bit 7
29,30
1
CLKT8,CLKC8
Bit 6
27,26
1
CLKT9,CLKC9
Bit 5
-
1
Reserved
Bit 4
-
1
Reserved
Bit 3
-
1
Reserved
Bit 2
-
1
Reserved
Bit 1
-
1
Reserved
Bit 0
-
1
Reserved
Byte 3: Reserved
(1=
enable, 0= disable)
BIT PIN# PWD
DESCRIPTION
Bit 7
-
1
Reserved
Bit 6
-
1
Reserved
Bit 5
-
1
Reserved
Bit 4
-
1
Reserved
Bit 3
-
1
Reserved
Bit 2
-
1
Reserved
Bit 1
-
1
Reserved
Bit 0
-
1
Reserved
Byte 5: Reserved
(1=
enable, 0= disable)
BIT
PIN# PWD
DESCRIPTION
Bit?
-
0
Reserved (Note)
Bit6
-
0
Reserved (Note)
BitS
-
0
Reserved (Note)
Bit4
-
0
Reserved (Note)
Bit3
-
0
Reserved (Note)
Bit2
-
1
Reserved (Note)
Bit1
-
1
Reserved (Note)
BitO
-
0
Reserved (Note)
Note: Don't write into this register, writing into this
register can cause malfunction



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