Electronic Components Datasheet Search
  British  ▼
ALLDATASHEET.CO.UK

X  

Preview PDF HTML

ICS93732 Datasheet(PDF) 2 Page - Renesas Technology Corp

Part # ICS93732
Description  Low Cost DDR Phase Lock Loop Zero Delay Buffer
PDF  9 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ICS93732 Datasheet(HTML) 2 Page - Renesas Technology Corp

  ICS93732 Datasheet HTML 1Page - Renesas Technology Corp ICS93732 Datasheet HTML 2Page - Renesas Technology Corp ICS93732 Datasheet HTML 3Page - Renesas Technology Corp ICS93732 Datasheet HTML 4Page - Renesas Technology Corp ICS93732 Datasheet HTML 5Page - Renesas Technology Corp ICS93732 Datasheet HTML 6Page - Renesas Technology Corp ICS93732 Datasheet HTML 7Page - Renesas Technology Corp ICS93732 Datasheet HTML 8Page - Renesas Technology Corp ICS93732 Datasheet HTML 9Page - Renesas Technology Corp  
Zoom Inzoom in Zoom Outzoom out
 2 / 9 page
background image
2
ICS93732
0578J—06/20/08
Pin Descriptions
PIN #
PIN NAME
PIN TYPE DESCRIPTION
1
DDRC0
OUT
"Complimentary" Clock of differential pair output.
2
DDRT0
OUT
"True" Clock of differential pair output.
3
VDD
PWR
Power supply, nominal 2.5V
4
DDRT1
OUT
"True" Clock of differential pair output.
5
DDRC1
OUT
"Complimentary" Clock of differential pair output.
6
GND
PWR
Ground pin.
7
SCLK
IN
Clock pin of I2C circuitry 5V tolerant
8
CLK_INT
IN
"True" reference clock input.
9
N/C
N/C
No Connection.
10
VDDA
PWR
2.5V power for the PLL core.
11
GND
PWR
Ground pin.
12
VDD
PWR
Power supply, nominal 2.5V
13
DDRT2
OUT
"True" Clock of differential pair output.
14
DDRC2
OUT
"Complimentary" Clock of differential pair output.
15
GND
PWR
Ground pin.
16
DDRC3
OUT
"Complimentary" Clock of differential pair output.
17
DDRT3
OUT
"True" Clock of differential pair output.
18
N/C
N/C
No Connection.
19
FB_OUT
OUT
Feedback output, dedicated for external feedback.
20
FB_INT
IN
True single-ended feedback input, provides feedback
signal to internal PLL for synchronization with CLK_INT
to eliminate phase error.
21
N/C
N/C
No Connection.
22
SDATA
I/O
Data pin for I2C circuitry 5V tolerant
23
VDD
PWR
Power supply, nominal 2.5V
24
DDRT4
OUT
"True" Clock of differential pair output.
25
DDRC4
OUT
"Complimentary" Clock of differential pair output.
26
DDRT5
OUT
"True" Clock of differential pair output.
27
DDRC5
OUT
"Complimentary" Clock of differential pair output.
28
GND
PWR
Ground pin.



Html Pages

1 2 3 4 5 6 7 8 9


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com