IDT, IDT logo and the

SyncFIFO logo are registered trademarks of Integrated Device Technology, Inc.

FEBRUARY 2018

DUAL CMOS SyncFIFO™

DUAL 256 x 9, DUAL 512 x 9,

DUAL 1,024 x 9, DUAL 2,048 x 9,

DUAL 4,096 x 9, DUAL 8,192 x 9

IDT72801

IDT72811

IDT72821

IDT72831

IDT72841

IDT72851

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

1

DSC-3034/7

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

FEATURES:

••••• The IDT72801 is equivalent to two IDT72201 256 x 9 FIFOs

••••• The IDT72811 is equivalent to two IDT72211 512 x 9 FIFOs

••••• The IDT72821 is equivalent to two IDT72221 1,024 x 9 FIFOs

••••• The IDT72831 is equivalent to two IDT72231 2,048 x 9 FIFOs

••••• The IDT72841 is equivalent to two IDT72241 4,096 x 9 FIFOs

••••• The IDT72851 is equivalent to two IDT72251 8,192 x 9 FIFOs

••••• Offers optimal combination of large capacity, high speed,

design flexibility and small footprint

••••• Ideal for prioritization, bidirectional, and width expansion

applications

••••• 10 ns read/write cycle time for the IDT72801/72811/72821/72831/

72841/72851

••••• Separate control lines and data lines for each FIFO

••••• Separate Empty, Full, Programmable Almost-Empty and Almost-

Full flags for each FIFO

••••• Enable puts output data lines in high-impedance state

••••• Space-saving 64-pin Thin Quad Flat Pack (TQFP) and Slim Thin

Quad Flatpack (STQFP)

• Industrial temperature range (–40

°°°°°C to +85°°°°°C) is available

••••• Green parts available, see ordering information

DESCRIPTION:

TheIDT72801/72811/72821/72831/72841/72851aredualsynchronous

(clocked)FIFOs. ThedeviceisfunctionallyequivalenttotwoIDT72201/72211/

72221/72231/72241/72251 FIFOs in a single package with all associated

control,data,andflaglinesassignedtoseparatepins.

Each of the two FIFOs (designated FIFO A and FIFO B) contained in the

IDT72801/72811/72821/72831/72841/72851hasa9-bitinputdataport(DA0

-DA8,DB0-DB8)anda9-bitoutputdataport(QA0-QA8,QB0-QB8).Each

inputportiscontrolledbyafree-runningclock(WCLKA,WCLKB),andtwoWrite

Enablepins(WENA1,WENA2,WENB1,WENB2). Dataiswrittenintoeachof

thetwoarraysoneveryrisingclockedgeoftheWriteClock(WCLKA,WCLKB)

when the appropriate write enable pins are asserted.

TheoutputportofeachFIFObankiscontrolledbyitsassociated clockpin

(RCLKA, RCLKB) and two Read Enable pins (RENA1, RENA2, RENB1,

RENB2).TheReadClockcanbetiedtotheWriteClockforsingleclockoperation

orthetwoclockscanrunasynchronousofoneanotherfordualclockoperation.

An Output Enable pin (OEA, OEB) is provided on the read port of each FIFO

forthree-stateoutputcontrol.

EachofthetwoFIFOshastwofixedflags,Empty(EFA,EFB)andFull(FFA,

FFB). Twoprogrammableflags,Almost-Empty(PAEA,PAEB)andAlmost-Full

(PAFA,PAFB),areprovidedforeachFIFObanktoimprovememoryutilization.

Ifnotprogrammed,theprogrammableflagsdefaulttoempty+7forPAEAand

PAEB, and full-7 for PAFA and PAFB.

TheIDT72801/72811/72821/72831/72841/72851architecturelendsitself

tomanyflexibleconfigurationssuchas:

• 2-levelprioritydatabuffering

• Bidirectional operation

• Width expansion

• Depthexpansion

These FIFOs is fabricated using high-performance submicron CMOS

technology.

FUNCTIONAL BLOCK DIAGRAM

WCLKA

WENA1

WENA2

DA0 - DA8

LDA

OFFSET REGISTER

INPUT REGISTER

RAM ARRAY

256 x 9, 512 x 9,

1024 x 9, 2048 x 9,

4096 x 9, 8192 x 9

WRITE CONTROL

LOGIC

WRITE POINTER

RESET LOGIC

OUTPUT REGISTER

OEA

RSA

QA0 - QA8

RCLKA

RENA1

RENA2

READ CONTROL

LOGIC

READ POINTER

FLAG

LOGIC

EFA

PAEA

PAFA

FFA

3034 drw 01

WCLKB

WENB1

WENB2

DB0 - DB8

LDB

OFFSET REGISTER

INPUT REGISTER

WRITE CONTROL

LOGIC

WRITE POINTER

RESET LOGIC

OUTPUT REGISTER

OEB

RSB

QB0 - QB8

RCLKB

RENB1

RENB2

READ CONTROL

LOGIC

READ POINTER

FLAG

LOGIC

EFB

PAEB

PAFB

FFB

RAM ARRAY

256 x 9, 512 x 9,

1024 x 9, 2048 x 9,

4096 x 9, 8192 x 9