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January 18, 2011

CPS-10Q

CPS-10Q Datasheet

2010 Integrated Device Technology, Inc. All rights reserved.

17 JTAG Interface

Description

The CPS-10Q offers full JTAG (Boundary Scan) support for both its slow speed and high speed pins. This allows “pins-down” testing of newly manu-

factured printed circuit boards as well as troubleshooting of field returns. The JTAG TAP interface also offers an alternative method for Configuration

Register Access (CRA) (along with the sRIO and I2C ports). Thus this port may be used for programming the device’s registers.

Boundary scan testing of the AC-coupled IOs is performed in accordance with IEEE 1149.6 (AC Extest).

IEEE 1149.1 (JTAG) & IEEE 1149.6 (AC Extest) Compliance

All DC pins are in full compliance with IEEE 1149.1 [10]. All AC-coupled pins fully comply with IEEE 1149.6 [11]. All 1149.1 and 1149.6 boundary scan

cells are on the same chain. No additional control cells are provided for independent selection of negative and/or positive terminals of the TX- or RX-

pairs.

System Logic TAP Controller Overview

The system logic utilizes a 16-state, six-bit TAP controller, a four-bit instruction register, and five dedicated pins to perform a variety of functions. The

primary use of the JTAG TAP Controller state machine is to allow the five external JTAG control pins to control and access the CPS-10Q's many

external signal pins. The JTAG TAP Controller can also be used for identifying the device part number. The JTAG logic of the device is depicted in the

figure below.

Figure 19 Diagram of the JTAG Logic

Bypass Register

Instruction Register Decoder

4-Bit Instruction Register

Tap Controller

m

u

x

m

u

x

Device ID Register

Boundary Scan Register

TDI

TMS

TCK

TRST

TDO