FXPS7115D4 datasheet(44/72 Pages) NXP

44 / 72 page

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Bit

Symbol

Description

5 to 4

INT_PS[1:0]

The INT_PS[1:0] bits set the programmable pulse stretch time for the interrupt output. Pulse stretch times are derived

from the internal oscillator, so the tolerance on this oscillator applies.

00 — 0 ms

01 —16.000 ms to 16.512 ms

10 — 64.000 ms to 64.512 ms

11 — 256.000 ms to 256.512 ms

If the pulse stretch function is programmed to '00', the interrupt pin is asserted if and only if the interrupt condition exists

after the most recent evaluated sample. The interrupt pin is deasserted if and only if an interrupt condition does not

exist after the most recent evaluated sample.

If the pulse stretch function is programmed to a non-zero value, the interrupt pin is controlled only by the value of the

pulse stretch timer value. If the pulse stretch timer value is non-zero, the interrupt pin is asserted. If the pulse stretch

timer is zero, the interrupt pin is deasserted. The pulse stretch counter continuously decrements until it reaches zero.

The pulse stretch counter is reset to the programmed pulse stretch value if and only if an interrupt condition exists after

the most recent evaluated sample.

INT_POLARITY

The interrupt polarity bit controls whether the interrupt is activated for values within or outside the window selected

by the high and low threshold registers. With this bit and the programmable thresholds, a window comparator can be

programmed for activation either within or outside a window.

0 — Interrupt activated, if the value is outside the window

1 — Interrupt activated, if the value is inside the window

Table 75. INT_CFG - interrupt configuration register (address 45h) bit description

7.7.13 P_INT_HI, P_INT_LO - interrupt window comparator threshold registers (address 46h to

49h)

The interrupt threshold registers contain the high and low window comparator thresholds for pressure to be

used to activate and deactivate the interrupt output. These registers can be written during initialization but are

locked once the ENDINIT bit is set (see Section 7.7.4 "DEVLOCK_WR - lock register writes register (address

10h)"). The register is included in the read/write array error detection.

Location

Bit

Address

46h

PIN_INT_HI_L

PIN_INT_HI[7:0]

47h

PIN_INT_HI_H

PIN_INT_HI[15:8]

48h

PIN_INT_LO_L

PIN_INT_LO[7:0]

49h

PIN_INT_LO_H

PIN_INT_LO[15:8]

Reset

Access

R/W

Table 76. P_INT_HI, P_INT_LO - interrupt window comparator threshold registers (address 46h to 49h) bit

allocation

The pressure threshold registers hold independent unsigned 16-bit values for a high and a low threshold. The

window comparator threshold alignment is shown in Section 7.3.3.4 "Absolute pressure output data scaling

equation".

If either the high or low threshold is programmed to 0000h, comparisons are disabled for that threshold only.

The interrupt comparison still functions for the opposite threshold. If both the high and low thresholds are

programmed to 0000h, the interrupt output is disabled.

7.7.14 P_CAL_ZERO - pressure calibration registers (address 4Ch, 4Dh)

The pressure calibration registers contain user programmable values to adjust the offset of the absolute

pressure.

These registers can be written during initialization but are locked once the ENDINIT bit is set (see Section 7.7.4

"DEVLOCK_WR - lock register writes register (address 10h)"). These registers are included in the read/write

array error detection. Changes to these registers reset the DSP data path. The contents of the SNSDATA_x

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6.2 — 28 June 2023

44 / 72

FXPS7115D4 Datasheet(PDF) 44 Page - NXP Semiconductors

FXPS7115D4 Datasheet(HTML) 44 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

Datasheet Download

Link URL