4

ICSSSTUB32S868D

Advance Information

08/14/06

General Description

This 28-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation. All inputs are compatible

with the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET)

inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet

SSTL_18 specifications, except the open-drain error (QERR) output.

The ICSSSTUB32S868D operates from a differential clock (CK and CK). Data are registered at the crossing of CK

going high and CK going low. The device supports low-power standby operation. When RESET is low, the differential

input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In

addition, when RESET is low, all registers are reset and all outputs are forced low except QERR. The LVCMOS RESET

and C inputs always must be held at a valid logic high or low level. To ensure defined outputs from the register before

a stable clock has been supplied, RESET must be held in the low state during power up. In the DDR2 RDIMM

application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing

relationship can be ensured between the two. When entering reset, the register will be cleared and the data outputs

will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of

reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as

the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input

receivers are fully enabled, the design of the ICSSSTUB32S868D must ensure that the outputs will remain low, thus

ensuring no glitches on the output.

Inpu ts

Output

RST#

DCS0#

DCS1#

CK

CK#

Σ of inputs = H

(D1 - D28)

PAR_I N

†

QERR#

‡

H

LX

Even

L

H

H

LX

Odd

L

L

HLX

Even

H

L

H

LX

Odd

H

H

H

XL

Even

L

H

H

X

L

Odd

L

L

H

XL

Even

H

L

H

XL

Odd

H

H

H

HH

XX

QERR#0 §

HX

X

L or H

L or H

X

X

QERR#0

L

X or

floating

X or

floating

X or

floating

X or

floating

X

X or

floating

H

↑

↑

↑

↑

↑

↑

↑

↑

↑

↓

↓

↓

↓

↓

↓

↓

↓

↓

†

PAR_IN arrives one clock cycle after the data to which it applies.

‡

This transition assumes QERR# is high at the crossing of CK going high and CK#

going low. If QERR# is low, it stays latches low for two clock cycles or until RST#

is driven low.

§ If DCS0#, DCS1#, and CSGEN are driven high, the device is placed in low-power mode

(LPM). If a parity error occurs on the clock cycle before the device enters the LPM and the

QERR# output is driven low, it stays latches low for the LPM duration plus two clock cycles

or until RST# is driven low.