Nexperia

74LVC2G74

Single D-type flip-flop with set and reset; positive edge trigger

mna421

SD

CP

RD

D

C

C

Q

C

C

C

C

C

C

Q

C

C

Fig. 3. Logic diagram

6. Pinning information

6.1. Pinning

74LVC2G74

CP

VCC

D

SD

Q

RD

GND

Q

001aaf642

1

2

3

4

6

5

8

7

Fig. 4. Pin configuration SOT505-2 (TSSOP8) and

SOT765-1 (VSSOP8)

74LVC2G74

RD

SD

VCC

Q

Q

D

CP

GND

001aaf643

3

6

2

7

1

8

4

5

Transparent top view

Fig. 5. Pin configuration SOT833-1, SOT1116 and

SOT1203 (XSON8)

6.2. Pin description

Table 3. Pin description

Symbol

Pin

Description

CP

1

clock input (LOW-to-HIGH, edge-triggered)

D

2

data input

Q

3

complement output

GND

4

ground (0 V)

Q

5

true output

RD

6

asynchronous reset-direct input (active LOW)

SD

7

asynchronous set-direct input (active LOW)

VCC

8

supply voltage

74LVC2G74

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Product data sheet

Rev. 14 — 27 August 2021

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