Nexperia

74HC240; 74HCT240

Octal buffer/line driver; 3-state; inverting

VM

VM

tW

tW

10 %

90 %

0 V

VI

VI

negative

pulse

positive

pulse

0 V

VM

VM

90 %

10 %

tf

tr

tr

tf

001aad983

DUT

VCC

VCC

VI

VO

RT

RL

S1

CL

open

G

Test data is given in Table 9.

Definitions test circuit:

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

CL = Load capacitance including jig and probe capacitance.

RL = Load resistance.

S1 = Test selection switch.

Fig. 8. Test circuit for measuring switching times

Table 9. Test data

Input

Load

S1 position

Type

VI

tr, tf

CL

RL

tPHL, tPLH

tPZH, tPHZ

tPZL, tPLZ

74HC240

VCC

6 ns

15 pF, 50 pF

1 kΩ

open

GND

VCC

74HCT240

3 V

6 ns

15 pF, 50 pF

1 kΩ

open

GND

VCC

74HC_HCT240

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 6 — 2 September 2021

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