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CS53L21 Datasheet(PDF) 17 Page - Cirrus Logic

Part # CS53L21
Description  Low Power, Stereo Analog to Digital Converter
PDF  66 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS53L21 Datasheet(HTML) 17 Page - Cirrus Logic

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DS700PP1
17
CS53L21
SWITCHING CHARACTERISTICS - SPI CONTROL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL)
12. Data must be held for sufficient time to bridge the transition time of CCLK.
13. For fsck <1 MHz.
Parameter
Symbol
Min
Max
Units
CCLK Clock Frequency
fsck
06.0
MHz
RESET Rising Edge to CS Falling
tsrs
20
-
ns
CS Falling to CCLK Edge
tcss
20
-
ns
CS High Time Between Transmissions
tcsh
1.0
-
μs
CCLK Low Time
tscl
66
-
ns
CCLK High Time
tsch
66
-
ns
CDIN to CCLK Rising Setup Time
tdsu
40
-
ns
CCLK Rising to DATA Hold Time
(Note 12)
tdh
15
-
ns
Rise Time of CCLK and CDIN
(Note 13)
tr2
-100
ns
Fall Time of CCLK and CDIN
(Note 13)
tf2
-100
ns
CS
CCLK
CDIN
RST
t
srs
t
scl
t
sch
t
css
t
r2
t
f2
t
csh
t
dsu
t
dh
Figure 6. Control Port Timing - SPI Format



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